Datasheet

PIC12F683
DS41211D-page 2 © 2007 Microchip Technology Inc.
8-Pin Diagram (PDIP, SOIC)
8-Pin Diagram (DFN)
8-Pin Diagram (DFN-S)
TABLE 1: 8-PIN SUMMARY
I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic
GP0 7 AN0 CIN+ — — IOC Y ICSPDAT/ULPWU
GP1 6 AN1/VREF CIN- — — IOC Y ICSPCLK
GP2 5 AN2 COUT T0CKI CCP1 INT/IOC Y —
GP3
(1)
4— — — — IOCY
(2)
MCLR/VPP
GP4 3 AN3 —
T1G
— IOC Y OSC2/CLKOUT
GP5 2 — — T1CKI — IOC Y OSC1/CLKIN
— 1 — — — — — — VDD
—8 — — — — — — VSS
Note 1: Input only.
2: Only when pin is configured for external MCLR.
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G
/OSC2/CLKOUT
GP3/MCLR
/VPP
VSS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP1/AN1/CIN-/V
REF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1
PIC12F683
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
8
PIC12F683
V
SS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP1/AN1/CIN-/V
REF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1
VDD
GP5/TICKI/OSC1/CLKIN
GP4/AN3/TIG
/OSC2/CLKOUT
GP3/MCLR
/VPP
1
2
3
4
5
6
7
8
PIC12F683
V
SS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP1/AN1/CIN-/V
REF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1
VDD
GP5/TICKI/OSC1/CLKIN
GP4/AN3/TIG
/OSC2/CLKOUT
GP3/MCLR
/VPP