Datasheet

© 2007 Microchip Technology Inc. DS41190E-page 23
PIC12F629/675
3.3.3 GP2/AN2/T0CKI/INT/COUT
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• the clock input for TMR0
• an external edge triggered interrupt
• a digital output from the comparator
FIGURE 3-2: BLOCK DIAGRAM OF GP2
3.3.4 GP3/MCLR/VPP
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset
FIGURE 3-3: BLOCK DIAGRAM OF GP3
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPU
RD
WPU
RD
PORT
WR
PORT
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
Interrupt-on-Change
To A/D Converter
0
1
COUT
COUT
Enable
To I N T
To T M R0
Analog
Input Mode
GPPU
RD PORT
Analog
Input
Mode
I/O pin
V
SS
D
Q
CK
Q
D
EN
Q
Data Bus
RD PORT
RD
PORT
WR
IOC
RD
IOC
Interrupt-on-Change
RESET
MCLRE
RD
TRISIO
VSS
D
EN
Q
MCLRE