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PIC12F629/675

Data Sheet

8-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450.

Additional U.S. and foreign patents and applications may be issued or pending.

Summary of content (128 pages)

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PIC12F629/675 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2007 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC12F629/675 8-Pin FLASH-Based 8-Bit CMOS Microcontroller High Performance RISC CPU: Low Power Features: • Only 35 instructions to learn - All single cycle instructions except branches • Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle • Interrupt capability • 8-level deep hardware stack • Direct, Indirect, and Relative Addressing modes • Standby Current: - 1 nA @ 2.0V, typical • Operating Current: - 8.5 μA @ 32 kHz, 2.0V, typical - 100 μA @ 1 MHz, 2.
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PIC12F629/675 Pin Diagrams DS41190E-page 2 1 GP5/T1CKI/OSC1/CLKIN 2 GP4/T1G/OSC2/CLKOUT 3 GP3/MCLR/VPP 4 VDD 1 GP5/T1CKI/OSC1/CLKIN 2 GP4/AN3/T1G/OSC2/CLKOUT 3 GP3/MCLR/VPP 4 PIC12F675 VDD PIC12F629 8-pin PDIP, SOIC, DFN-S 8 VSS 7 GP0/CIN+/ICSPDAT 6 GP1/CIN-/ICSPCLK 5 GP2/T0CKI/INT/COUT 8 VSS 7 GP0/AN0/CIN+/ICSPDAT 6 GP1/AN1/CIN-/VREF/ICSPCLK 5 GP2/AN2/T0CKI/INT/COUT © 2007 Microchip Technology Inc.
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PIC12F629/675 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization.................................................................................................................................................................. 7 3.0 GPIO Port ......................................................................................
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PIC12F629/675 1.0 DEVICE OVERVIEW Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. This document contains device specific information for the PIC12F629/675. Additional information may be found in the PIC® Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site.
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PIC12F629/675 TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION Name GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/VREF/ ICSPCLK GP2/AN2/T0CKI/INT/COUT GP3/MCLR/VPP GP4/AN3/T1G/OSC2/ CLKOUT GP5/T1CKI/OSC1/CLKIN VSS VDD Legend: Function Input Type Output Type GP0 TTL CMOS AN0 CIN+ ICSPDAT GP1 AN AN TTL TTL CMOS CMOS AN1 CINVREF ICSPCLK GP2 AN AN AN ST ST CMOS AN2 T0CKI INT COUT AN ST ST GP3 TTL Input port w/ interrupt-on-change MCLR VPP ST HV Master Clear Programming voltage GP4 TTL AN3 AN T1G
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PIC12F629/675 2.0 MEMORY ORGANIZATION 2.2 2.1 Program Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose registers and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank. Register locations 20h-5Fh are General Purpose registers, implemented as static RAM and are mapped across both banks. All other RAM is unimplemented and returns ‘0’ when read.
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PIC12F629/675 2.2.2 SPECIAL FUNCTION REGISTERS FIGURE 2-2: The Special Function registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. DATA MEMORY MAP OF THE PIC12F629/675 File Address Indirect addr.(1) TMR0 PCL STATUS FSR GPIO The special registers can be classified into two sets: core and peripheral. The Special Function registers associated with the “core” are described in this section.
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PIC12F629/675 TABLE 2-1: Address SPECIAL FUNCTION REGISTERS SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Page Bank 0 00h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 18,59 01h TMR0 Timer0 Module’s Register xxxx xxxx 27 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 17 03h STATUS 04h FSR 05h GPIO IRP(2) RP1(2) RP0 TO PD Z DC C Indirect Data Memory Address Pointer — --xx xxxx
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PIC12F629/675 TABLE 2-1: Address SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PS1 PS0 Value on POR, BOD Page 0000 0000 18,59 1111 1111 12,28 0000 0000 17 0001 1xxx 11 xxxx xxxx 18 --11 1111 19 Bank 1 80h INDF(1) 81h OPTION_REG 82h PCL 83h STATUS 84h FSR 85h TRISIO Addressing this Location uses Contents of FSR to Address Data Memory GPPU INTEDG T0CS T0SE PSA PS2 Program Counter's (PC) Least Significant Byte IRP
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PIC12F629/675 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the RESET status • the bank select bits for data memory (SRAM) It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bits. For other instructions not affecting any STATUS bits, see the “Instruction Set Summary”.
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PIC12F629/675 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure: • • • • TMR0/WDT prescaler External GP2/INT interrupt TMR0 Weak pull-ups on GPIO REGISTER 2-2: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to ‘1’ (OPTION<3>). See Section 4.4.
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PIC12F629/675 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO port change and external GP2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
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PIC12F629/675 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
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PIC12F629/675 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC12F629/675 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Detect (BOD) Watchdog Timer Reset (WDT) External MCLR Reset The PCON Register bits are shown in Register 2-6.
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PIC12F629/675 2.3 PCL and PCLATH 2.3.2 The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any RESET, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
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PIC12F629/675 2.4 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 2-1: Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select register (FSR). Reading INDF itself indirectly will produce 00h.
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PIC12F629/675 3.0 GPIO PORT register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Note: 3.
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PIC12F629/675 REGISTER 3-2: TRISIO — GPIO TRI-STATE REGISTER (ADDRESS: 85h) U-0 — U-0 R/W-x R/W-x R-1 — TRISIO5 TRISIO4 TRISIO3 R/W-x R/W-x TRISIO2 TRISIO1 R/W-x TRISIO0 bit 7 bit 0 bit 7-6: Unimplemented: Read as ’0’ bit 5-0: TRISIO<5:0>: General Purpose I/O Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output. Note: TRISIO<3> always reads 1.
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PIC12F629/675 3.2.2 INTERRUPT-ON-CHANGE Each of the GPIO pins is individually configurable as an interrupt-on-change pin. Control bits IOC enable or disable the interrupt function for each pin. Refer to Register 3-4. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of GPIO.
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PIC12F629/675 3.3 Pin Descriptions and Diagrams Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. 3.3.1 GP0/AN0/CIN+ Figure 3-1 shows the diagram for this pin.
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PIC12F629/675 3.3.3 GP2/AN2/T0CKI/INT/COUT 3.3.4 GP3/MCLR/VPP Figure 3-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: Figure 3-3 shows the diagram for this pin.
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PIC12F629/675 3.3.5 GP4/AN3/T1G/OSC2/CLKOUT 3.3.6 GP5/T1CKI/OSC1/CLKIN Figure 3-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: Figure 3-5 shows the diagram for this pin.
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PIC12F629/675 TABLE 3-1: Address SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOD Value on all other RESETS 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u 19h CMCON — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISIO —
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PIC12F629/675 4.0 TIMER0 MODULE Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge.
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PIC12F629/675 4.3 Using Timer0 with an External Clock a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks.
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PIC12F629/675 4.4 Prescaler EXAMPLE 4-1: An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as “prescaler” throughout this Data Sheet. The prescaler assignment is controlled in software by the control bit PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS2:PS0 bits (OPTION_REG<2:0>).
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PIC12F629/675 5.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 Control register (T1CON), shown in Register 5-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. The PIC12F629/675 devices have a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • • • • • • • • Note: Additional information on timer modules is available in the PIC® Mid-Range Reference Manual, (DS33023).
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PIC12F629/675 5.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit timer with prescaler • 16-bit synchronous counter • 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously.
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PIC12F629/675 REGISTER 5-1: T1CON — TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 — R/W-0 R/W-0 R/W-0 R/W-0 TMR1GE T1CKPS1 T1CKPS0 T1OSCEN R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if T1G pin is low 0 = Timer1 is on bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Va
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PIC12F629/675 5.4 Timer1 Operation in Asynchronous Counter Mode 5.5 If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 5.4.1). Note: 5.4.
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PIC12F629/675 6.0 COMPARATOR MODULE be applied to an input of the comparator. In addition, GP2 can be configured as the comparator output. The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator. The PIC12F629/675 devices have one analog comparator. The inputs to the comparator are multiplexed with the GP0 and GP1 pins.
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PIC12F629/675 6.1 Comparator Operation A single comparator is shown in Figure 6-1, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
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PIC12F629/675 6.2 Comparator Configuration There are eight modes of operation for the comparator. The CMCON register, shown in Register 6-1, is used to select the mode. Figure 6-2 shows the eight possible modes. The TRISIO register controls the data direction of the comparator pins for each mode. If the FIGURE 6-2: Comparator mode is changed, the comparator output level may not be valid for a specified period of time. Refer to the specifications in Section 12.0.
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PIC12F629/675 6.3 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latchup may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 6-3.
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PIC12F629/675 6.5 Comparator Reference The following equations determine the output voltages: The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The internal reference signal is used for four of the eight Comparator modes. The VRCON register, Register 6-2, controls the voltage reference module shown in Figure 6-5. 6.5.
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PIC12F629/675 REGISTER 6-2: VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN — VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain bit 6 Unimplemented: Read as '0' bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as '0' bit 3-0 VR3:VR0: CVREF value selection 0 ≤ VR [3:0] ≤ 15 When VRR = 1: CVREF
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PIC12F629/675 7.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE (PIC12F675 ONLY) The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. Figure 7-1 shows the block diagram of the A/D on the PIC12F675.
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PIC12F629/675 TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES A/D Clock Source (TAD) Device Frequency Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz 2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 μs 4 TOSC 100 200 ns(2) 800 ns(2) 1.0 μs(2) 3.2 μs 8 TOSC 001 400 ns(2) 1.6 μs 2.0 μs 6.4 μs (2) 16 TOSC 101 800 ns 3.2 μs 4.0 μs 12.8 μs(3) (3) 32 TOSC 010 1.6 μs 6.4 μs 8.0 μs 25.6 μs(3) (3) (3) 64 TOSC 110 3.2 μs 12.8 μs 16.0 μs 51.
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PIC12F629/675 REGISTER 7-1: ADCON0 — A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5-4 Unimplemented: Read as zero bit 3-2 CHS1:CHS0: Analog Channel Select bits 00 = Channel 00 (AN0) 01 = Channel 01 (AN1) 10 = Channel 02 (AN2) 11 = Channel 03 (AN3) bit 1 GO/DONE
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PIC12F629/675 REGISTER 7-2: ANSEL — ANALOG SELECT REGISTER (ADDRESS: 9Fh) U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’.
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PIC12F629/675 7.2 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 7-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 7-3.
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PIC12F629/675 7.3 A/D Operation During SLEEP The A/D converter module can operate during SLEEP. This requires the A/D clock source to be set to the internal RC oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/DONE bit is cleared, and the result is loaded into the ADRESH:ADRESL registers.
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PIC12F629/675 8.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write).
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PIC12F629/675 8.1 EEADR The EEADR register can address up to a maximum of 128 bytes of data EEPROM. Only seven of the eight bits in the register (EEADR<6:0>) are required. The MSb (bit 7) is ignored. The upper bit should always be ‘0’ to remain upward compatible with devices that have more data EEPROM memory. 8.2 EECON1 AND EECON2 REGISTERS EECON1 is the control register with four low order bits physically implemented. The upper four bits are nonimplemented and read as '0's.
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PIC12F629/675 8.3 READING THE EEPROM DATA MEMORY To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), as shown in Example 8-1. The data is available, in the very next cycle, in the EEDATA register. Therefore, it can be read in the next instruction. EEDATA holds this value until another read, or until it is written to by the user (during a write operation). EXAMPLE 8-1: bsf movlw movwf bsf movf 8.
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PIC12F629/675 8.7 DATA EEPROM OPERATION DURING CODE PROTECT Data memory can be code protected by programming the CPD bit to ‘0’. When the data memory is code protected, the CPU is able to read and write data to the Data EEPROM. It is recommended to code protect the program memory when code protecting data memory.
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PIC12F629/675 9.0 SPECIAL FEATURES OF THE CPU Certain special circuits that deal with the needs of real time applications are what sets a microcontroller apart from other processors.
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PIC12F629/675 9.1 Configuration Bits Note: The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1') to select various device configurations, as shown in Register 9-1. These bits are mapped in program memory location 2007h.
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PIC12F629/675 9.2 Oscillator Configurations 9.2.1 LP Low Power Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor (2 modes) INTOSC Internal Oscillator (2 modes) EC External Clock In Note: Additional information on oscillator configurations is available in the PIC® MidRange Reference Manual, (DS33023). 9.2.
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PIC12F629/675 9.2.3 EXTERNAL CLOCK IN 9.2.5 For applications where a clock is already available elsewhere, users may directly drive the PIC12F629/ 675 provided that this external clock source meets the AC/DC timing requirements listed in Section 12.0. Figure 9-2 shows how an external clock circuit should be configured. 9.2.4 RC OSCILLATOR For applications where precise timing is not a requirement, the RC oscillator option is available.
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PIC12F629/675 9.3 RESET The PIC12F629/675 differentiates between various kinds of RESET: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during SLEEP MCLR Reset during normal operation MCLR Reset during SLEEP Brown-out Detect (BOD) A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 9-4. Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in any other RESET.
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PIC12F629/675 9.3.1 MCLR PIC12F629/675 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event.
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PIC12F629/675 9.3.5 BROWN-OUT DETECT (BOD) On any RESET (Power-on, Brown-out, Watchdog, etc.), the chip will remain in RESET until VDD rises above BVDD (see Figure 9-6). The Power-up Timer will now be invoked, if enabled, and will keep the chip in RESET an additional 72 ms. The PIC12F629/675 members have on-chip Brown-out Detect circuitry. A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Detect circuitry.
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PIC12F629/675 TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Oscillator Configuration Brown-out Detect Wake-up from SLEEP PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP TPWRT + 1024•TOSC 1024•TOSC TPWRT + 1024•TOSC 1024•TOSC 1024•TOSC RC, EC, INTOSC TPWRT — TPWRT — — TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOD TO PD 0 u 1 1 Power-on Reset 1 0 1 1 Brown-out Detect u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal o
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PIC12F629/675 TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS • MCLR Reset during normal operation • MCLR Reset during SLEEP • WDT Reset • Brown-out Detect(1) • Wake-up from SLEEP through interrupt • Wake-up from SLEEP through WDT time-out Address Power-on Reset — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h — — — TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu
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PIC12F629/675 FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal RESET FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal RESET FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal RESET DS41190E-page 60 © 2007 Microchip Technology Inc.
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PIC12F629/675 9.4 Interrupts The PIC12F629/675 has 7 sources of interrupt: • • • • • • • External Interrupt GP2/INT TMR0 Overflow Interrupt GPIO Change Interrupts Comparator Interrupt A/D Interrupt (PIC12F675 only) TMR1 Overflow Interrupt EEPROM Data Write Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits.
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PIC12F629/675 FIGURE 9-10: INTERRUPT LOGIC IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR1IF TMR1IE CMIF CMIE ADIF ADIE T0IF T0IE Wake-up (If in SLEEP mode) INTF INTE GPIF GPIE Interrupt to CPU PEIE (1) GIE EEIF EEIE Note 1: PIC12F675 only. DS41190E-page 62 © 2007 Microchip Technology Inc.
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PIC12F629/675 9.4.1 GP2/INT INTERRUPT 9.4.2 An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 4.0. External interrupt on GP2/INT pin is edge-triggered; either rising if INTEDG bit (OPTION<6>) is set, of falling, if INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, the INTF bit (INTCON<1>) is set.
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PIC12F629/675 TABLE 9-8: Address SUMMARY OF INTERRUPT REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 0Bh, 8Bh INTCON GIE PEIE T0IE 0Ch PIR1 EEIF ADIF — 8Ch PIE1 EEIE ADIE — Value on all other RESETS Bit 0 Value on POR, BOD GPIF 0000 0000 0000 000u Bit 3 Bit 2 Bit 1 INTE GPIE T0IF INTF — CMIF — — TMR1IF 00-- 0--0 00-- 0--0 — CMIE — — TMR1IE 00-- 0--0 00-- 0--0 Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
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PIC12F629/675 FIGURE 9-12: WATCHDOG TIMER BLOCK DIAGRAM CLKOUT (= FOSC/4) Data Bus 0 8 1 SYNC 2 Cycles 1 T0CKI pin T0CS T0SE TMR0 0 0 8-bit Prescaler Set Flag bit T0IF on Overflow PSA 1 8 PSA 1 PS0 - PS2 WDT Time-out Watchdog Timer 0 PSA WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register. TABLE 9-9: Address SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 81h OPTION_REG GPPU INTEDG 2007h Config.
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PIC12F629/675 9.7 Power-Down Mode (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running PD bit in the STATUS register is cleared TO bit is set Oscillator driver is turned off I/O ports maintain the status they had before SLEEP was executed (driving high, low, or hi-impedance).
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PIC12F629/675 9.8 Code Protection FIGURE 9-14: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: 9.9 The entire data EEPROM and FLASH program memory will be erased when the code protection is turned off. The INTOSC calibration data is also erased. See PIC12F629/675 Programming Specification for more information.
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PIC12F629/675 10.0 INSTRUCTION SET SUMMARY The PIC12F629/675 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC12F629/675 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction.
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PIC12F629/675 TABLE 10-2: PIC12F629/675 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f
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PIC12F629/675 10.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [label] ADDLW Syntax: [label] BCF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) + k → (W) 0 ≤ f ≤ 127 0≤b≤7 Status Affected: C, DC, Z Operation: 0 → (f) Description: The contents of the W register are added to the eight-bit literal 'k' and the result is placed in the W register. Status Affected: None Description: Bit 'b' in register 'f' is cleared.
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PIC12F629/675 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 2047 Operands: None Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Operation: Status Affected: None 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
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PIC12F629/675 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register.
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PIC12F629/675 MOVF Move f NOP No Operation Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: No operation Operation: (f) → (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself.
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PIC12F629/675 RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
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PIC12F629/675 SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [label] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Operation: (W) .XOR. (f) → (destination) Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in the W register.
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PIC12F629/675 11.
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PIC12F629/675 11.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
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PIC12F629/675 11.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
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PIC12F629/675 11.11 PICSTART Plus Development Programmer 11.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
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PIC12F629/675 12.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings† Ambient temperature under bias........................................................................................................... -40 to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ...............................................................................................
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PIC12F629/675 FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.
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PIC12F629/675 FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +125°C 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.2 2.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. © 2007 Microchip Technology Inc.
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PIC12F629/675 12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) DC CHARACTERISTICS Param No. Sym VDD Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Units Supply Voltage D001 D001A D001B D001C D001D — — — — — 5.5 5.5 5.5 5.5 5.5 V V V V V 1.
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PIC12F629/675 12.2 DC Characteristics: PIC12F629/675-I (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. D010 Conditions Device Characteristics Min Typ† Max Units Supply Current (IDD) — 9 16 μA 2.0 — 18 28 μA 3.0 D011 D012 D013 D014 D015 D016 D017 VDD — 35 54 μA 5.0 — 110 150 μA 2.0 — 190 280 μA 3.0 — 330 450 μA 5.0 — 220 280 μA 2.0 — 370 650 μA 3.0 — 0.6 1.
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PIC12F629/675 12.3 DC Characteristics: PIC12F629/675-I (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. D020 Conditions Device Characteristics Min Typ† Max Units Power-down Base Current (IPD) — 0.99 700 nA 2.0 — 1.2 770 nA 3.0 — 2.9 995 nA 5.0 — 0.3 1.5 μA 2.0 — 1.8 3.5 μA 3.0 — 8.4 17 μA 5.0 — 58 70 μA 3.0 — 109 130 μA 5.0 — 3.3 6.5 μA 2.0 — 6.1 8.5 μA 3.0 — 11.
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PIC12F629/675 12.4 DC Characteristics: PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Param No. Device Characteristics Min Typ† Max Units D010E Supply Current (IDD) — 9 16 μA 2.0 — 18 28 μA 3.0 D011E D012E D013E D014E D015E D016E D017E VDD — 35 54 μA 5.0 — 110 150 μA 2.0 — 190 280 μA 3.0 — 330 450 μA 5.0 — 220 280 μA 2.0 — 370 650 μA 3.0 — 0.6 1.
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PIC12F629/675 12.5 DC Characteristics: PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Param No. D020E Conditions Device Characteristics Min Typ† Max Units Power-down Base Current (IPD) — 0.00099 3.5 μA 2.0 — 0.0012 4.0 μA 3.0 — 0.0029 8.0 μA 5.0 — 0.3 6.0 μA 2.0 — 1.8 9.0 μA 3.0 — 8.4 20 μA 5.0 — 58 70 μA 3.0 — 109 130 μA 5.0 — 3.3 10 μA 2.0 — 6.1 13 μA 3.
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PIC12F629/675 12.6 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Sym No.
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PIC12F629/675 12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No.
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PIC12F629/675 12.8 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
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PIC12F629/675 12.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED) FIGURE 12-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKOUT TABLE 12-1: Param No. Sym FOSC EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic Min Typ† Max Units External CLKIN Frequency(1) DC DC DC DC 5 — DC 0.
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PIC12F629/675 TABLE 12-2: Param No. F10 F14 Sym PRECISION INTERNAL OSCILLATOR PARAMETERS Characteristic FOSC Internal Calibrated INTOSC Frequency Freq Min Tolerance Typ† Max Units MHz VDD = 3.5V, 25°C MHz 2.5V ≤ VDD ≤ 5.5V 0°C ≤ TA ≤ +85°C MHz 2.0V ≤ VDD ≤ 5.5V -40°C ≤ TA ≤ +85°C (IND) -40°C ≤ TA ≤ +125°C (EXT) μs VDD = 2.0V, -40°C to +85°C μs VDD = 3.0V, -40°C to +85°C μs VDD = 5.0V, -40°C to +85°C ±1 ±2 3.96 3.92 4.00 4.00 4.04 4.08 ±5 3.80 4.00 4.
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PIC12F629/675 FIGURE 12-6: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 19 14 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param No.
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PIC12F629/675 FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset 34 31 34 I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD BVDD (Device not in Brown-out Detect) (Device in Brown-out Detect) 35 RESET (due to BOD) 72 ms time-out(1) Note 1: 72 ms delay only if PWRTE bit in configuration word is programmed to ‘0’.
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PIC12F629/675 TABLE 12-4: Param No.
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PIC12F629/675 FIGURE 12-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 48 47 TMR0 or TMR1 TABLE 12-5: Param No. 40* TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Sym Tt0H Characteristic T0CKI High Pulse Width Min No Prescaler With Prescaler 41* Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* Tt0P T0CKI Period 45* Tt1H T1CKI High Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous 46* Tt1L T1CKI Low Time — ns — — ns 0.
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PIC12F629/675 TABLE 12-6: COMPARATOR SPECIFICATIONS Comparator Specifications Sym Characteristics Standard Operating Conditions -40°C to +125°C (unless otherwise stated) Min Typ Max Units VOS Input Offset Voltage — ± 5.0 ± 10 mV VCM Input Common Mode Voltage 0 — VDD - 1.5 V CMRR Common Mode Rejection Ratio +55* — — db TRT Response Time(1) — 150 400* ns TMC2COV Comparator Mode Change to Output Valid — — 10* μs Comments * These parameters are characterized but not tested.
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PIC12F629/675 TABLE 12-8: Param No. Sym PIC12F675 A/D CONVERTER CHARACTERISTICS: Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10 bits A02 EABS Total Absolute Error* — — ±1 LSb VREF = 5.0V bit A03 EIL Integral Error — — ±1 LSb VREF = 5.0V A04 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.0V A05 EFS Full Scale Range 2.2* — 5.5* A06 EOFF Offset Error — — ±1 LSb VREF = 5.
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PIC12F629/675 FIGURE 12-10: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 1 TCY (TOSC/2)(1) 134 131 Q4 130 A/D CLK 9 A/D DATA 8 7 3 6 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO DONE SAMPLING STOPPED 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 12-9: Param No.
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PIC12F629/675 FIGURE 12-11: PIC12F675 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO 134 (TOSC/2 + TCY)(1) 1 TCY 131 Q4 130 A/D CLK 9 A/D DATA 8 7 3 6 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF 1 TCY GO DONE SAMPLE SAMPLING STOPPED 132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Param No.
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PIC12F629/675 13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
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PIC12F629/675 FIGURE 13-3: TYPICAL IPD vs. VDD OVER TEMP (+125°C) Typical Baseline IPD 4.0E-06 3.5E-06 IPD (A) 3.0E-06 2.5E-06 125 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-4: MAXIMUM IPD vs. VDD OVER TEMP (-40°C TO +25°C) Maximum Baseline IPD 1.0E-07 9.0E-08 IPD (A) 8.0E-08 7.0E-08 6.0E-08 -40 5.0E-08 0 4.0E-08 25 3.0E-08 2.0E-08 1.0E-08 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.
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PIC12F629/675 FIGURE 13-5: MAXIMUM IPD vs. VDD OVER TEMP (+85°C) Maximum Baseline IPD 9.0E-07 8.0E-07 IPD (A) 7.0E-07 6.0E-07 5.0E-07 4.0E-07 85 3.0E-07 2.0E-07 1.0E-07 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-6: MAXIMUM IPD vs. VDD OVER TEMP (+125°C) Maximum Baseline IPD 9.0E-06 8.0E-06 IPD (A) 7.0E-06 6.0E-06 5.0E-06 125 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc.
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PIC12F629/675 FIGURE 13-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical BOD IPD 130 120 IPD (uA) 110 -40 100 0 90 25 80 85 125 70 60 50 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-8: TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical Comparator IPD 1.8E-05 1.6E-05 1.4E-05 -40 IPD (A) 1.2E-05 0 1.0E-05 25 8.0E-06 85 6.0E-06 125 4.0E-06 2.0E-06 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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PIC12F629/675 FIGURE 13-9: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C) IPD (A) Typical A/D IPD 5.0E-09 4.5E-09 4.0E-09 3.5E-09 3.0E-09 2.5E-09 2.0E-09 1.5E-09 1.0E-09 5.0E-10 0.0E+00 -40 0 25 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-10: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C) Typical A/D IPD 3.5E-07 3.0E-07 IPD (A) 2.5E-07 2.0E-07 85 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) © 2007 Microchip Technology Inc.
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PIC12F629/675 FIGURE 13-11: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C) Typical A/D IPD 3.5E-06 IPD (A) 3.0E-06 2.5E-06 2.0E-06 125 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-12: TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C), 32 KHZ, C1 AND C2=50 pF) Typical T1 IPD 1.20E-05 1.00E-05 -40 IPD (A) 8.00E-06 0 25 6.00E-06 85 4.00E-06 125 2.00E-06 0.00E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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PIC12F629/675 FIGURE 13-13: TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical CVREF IPD 160 IPD (uA) 140 -40 120 0 25 100 85 80 125 60 40 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-14: TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical WDT IPD 16 IPD (uA) 14 12 -40 10 0 8 25 6 85 4 125 2 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD (V) © 2007 Microchip Technology Inc.
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PIC12F629/675 FIGURE 13-15: MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1μF AND 0.01μF DECOUPLING (VDD = 3.5V) Internal Oscillator Frequency vs Temperature 4.20E+06 Frequency (Hz) 4.15E+06 4.10E+06 4.05E+06 -3sigma 4.00E+06 average 3.95E+06 +3sigma 3.90E+06 3.85E+06 3.80E+06 -40°C 0°C 25°C 85°C 125°C Temperature (°C) FIGURE 13-16: MAXIMUM AND MINIMUM INTOSC FREQ vs. VDD WITH 0.1μF AND 0.01μF DECOUPLING (+25°C) Internal Oscillator Frequency vs VDD Frequency (Hz) 4.20E+06 4.
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PIC12F629/675 TYPICAL WDT PERIOD vs. VDD (-40°C TO +125°C) FIGURE 13-17: WDT Time-out 50 Time (mS) 45 40 35 -40 30 25 0 20 15 10 5 85 25 125 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD (V) © 2007 Microchip Technology Inc.
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PIC12F629/675 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 8-Lead PDIP (Skinny DIP) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC 12F629-I /017 e3 0215 Example XXXXXXXX XXXXYYWW NNN 8-Lead DFN-S XXXXXXX XXXXXXX XXYYWW NNN 12F629-E /0215 e3 017 Example 12F629 -E/021 e3 0215 017 Legend: XX...
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PIC12F629/675 14.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .
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PIC12F629/675 8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 Units Dimension Limits Number of Pins β MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.
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PIC12F629/675 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e D L b N N K E E2 EXPOSED PAD NOTE 1 1 2 2 NOTE 1 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A 0.80 1.27 BSC 0.85 1.00 Standoff A1 0.00 0.01 0.
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PIC12F629/675 APPENDIX A: DATA SHEET REVISION HISTORY Revision A APPENDIX B: DEVICE DIFFERENCES The differences between the PIC12F629/675 devices listed in this data sheet are shown in Table B-1. This is a new data sheet. Revision B Added characterization graphs. Updated specifications.
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PIC12F629/675 APPENDIX C: DEVICE MIGRATIONS This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable APPENDIX D: This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX family of devices. D.
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PIC12F629/675 INDEX A A/D ...................................................................................... 41 Acquisition Requirements ........................................... 45 Block Diagram............................................................. 41 Calculating Acquisition Time....................................... 45 Configuration and Operation....................................... 41 Effects of a RESET .....................................................
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PIC12F629/675 BSF ............................................................................. 71 BTFSC ........................................................................ 71 BTFSS ........................................................................ 71 CALL ........................................................................... 72 CLRF........................................................................... 72 CLRW .........................................................................
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PIC12F629/675 Prescaler..................................................................... 31 Timer1 Module with Gate Control ....................................... 30 Timing Diagrams CLKOUT and I/O......................................................... 96 External Clock............................................................. 94 INT Pin Interrupt.......................................................... 63 PIC12F675 A/D Conversion (Normal Mode).............
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PIC12F629/675 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC12F629/675 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC12F629/675 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern a) PIC12F629-E/P 301 = Extended Temp., PDIP b) PIC12F675-I/SN = Industrial Temp.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.