Datasheet

PIC12F629/675
DS41190G-page 48 2010 Microchip Technology Inc.
7.3 A/D Operation During Sleep
The A/D converter module can operate during Sleep.
This requires the A/D clock source to be set to the
internal RC oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE
bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from Sleep. If
the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.4 Effects of Reset
A device Reset forces all registers to their Reset state.
Thus the A/D module is turned off and any pending
conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
TABLE 7-2: SUMMARY OF A/D REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOD
Value on
all other
Resets
05h GPIO
GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx --uu uuuu
0Bh, 8Bh INTCON GIE PEIE
T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1
EEIF ADIF CMIF TMR1IF 00-- 0--0 00-- 0--0
1Eh ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result xxxx xxxx uuuu uuuu
1Fh ADCON0 ADFM VCFG
CHS1 CHS0 GO ADON 00-- 0000 00-- 0000
85h TRISIO
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
8Ch PIE1
EEIE ADIE CMIE TMR1IE 00-- 0--0 00-- 0--0
9Eh ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result xxxx xxxx uuuu uuuu
9Fh ANSEL
ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as
0’. Shaded cells are not used for A/D converter module.