Datasheet

 2010 Microchip Technology Inc. DS41190G-page 43
PIC12F629/675
7.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC12F675 ONLY)
The Analog-to-Digital converter (A/D) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. The PIC12F675 has four
analog inputs, multiplexed into one sample and hold
circuit. The output of the sample and hold is connected
to the input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a 10-bit register. The voltage reference
used in the conversion is software selectable to either
V
DD or a voltage applied by the VREF pin. Figure 7-1
shows the block diagram of the A/D on the PIC12F675.
FIGURE 7-1: A/D BLOCK DIAGRAM
7.1 A/D Configuration and Operation
There are two registers available to control the
functionality of the A/D module:
1. ADCON0 (Register 7-1)
2. ANSEL (Register 7-2)
7.1.1 ANALOG PORT PINS
The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO
bits control the operation of the A/D port pins. Set the
corresponding TRISIO bits to set the pin output driver
to its high-impedance state. Likewise, set the
corresponding ANS bit to disable the digital input
buffer.
7.1.2 CHANNEL SELECTION
There are four analog channels on the PIC12F675,
AN0 through AN3. The CHS1:CHS0 bits
(ADCON0<3:2>) control which channel is connected to
the sample and hold circuit.
7.1.3 VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converter: either V
DD is used, or an analog voltage
applied to V
REF is used. The VCFG bit (ADCON0<6>)
controls the voltage reference selection. If VCFG is set,
then the voltage on the V
REF pin is the reference;
otherwise, V
DD is the reference.
7.1.4 CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ANSEL<6:4>). There are seven possible
clock options:
•F
OSC/2
•FOSC/4
•F
OSC/8
•FOSC/16
•FOSC/32
•F
OSC/64
•FRC (dedicated internal RC oscillator)
For correct conversion, the A/D conversion clock
(1/T
AD) must be selected to ensure a minimum TAD of
1.6 s. Table 7-1 shows a few T
AD calculations for
selected frequencies.
GP0/AN0
ADC
GP1/AN1/VREF
GP2/AN2
GP4/AN3
VDD
VREF
ADON
GO/DONE
VCFG = 1
VCFG = 0
CHS1:CHS0
ADRESH ADRESL
10
10
ADFM
VSS
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.