Information

© 2009 Microchip Technology Inc. DS80125H-page 3
PIC12F629/675
Silicon Errata Issues
1. Module: Data EEPROM Memory
The EEIF flag may be cleared inadvertently when
performing operations on the PIR1 register,
simultaneously with the completion of an EEPROM
write. This condition occurs when the EEPROM
write timer completes at the same moment that the
PIR1 register operation is executed. Register
operations are those that have the PIR1 register as
the destination and include, but are not limited to,
BSF, BCF, ANDWF, IORWF and XORWF.
Work around
1. Avoid operations on the PIR1 register when
writing to the EEPROM memory.
2. Poll the WR bit (EECON1<1>) to determine
when the write is complete.
3. Use a timer interrupt to catch any instances
when the EEIF flag is inadvertently cleared.
The timer interrupt should be set longer than
8 ms. If EEIF fails, then the timer interrupt
occurs as a default time out. The WR and
WRERR flags are checked as part of the timer
Interrupt Service Routine to verify the
EEPROM write success.
4. If periodic interrupts are occurring in addition to
the EEIF interrupts, then use a secondary flag
to sense write completion. The secondary flag
is set whenever EEPROM writes are active. An
EEPROM write completion is indicated when
the secondary flag is set and the WR flag is
clear.
Affected Silicon Revisions
2. Module: Power-on Reset (Rising VDD
Detect)
The PIC12F629/675 Power-on Reset (POR)
circuitry is sensitive to a low V
DD level and may fail
to release the Reset if V
DD returns to an operational
voltage after dropping to a very low level.
The sensitive V
DD condition occurs when VDD
drops into an out-of-specification voltage region
below the Brown-out Detect threshold and then
recovers to a normal operating condition. The
voltage region that can cause the problem is
dependant upon temperature with the region
growing as the temperature drops. A typical region
is between 0.5 and 0.7V at -25°C. Below the region,
the POR operates correctly. Above the region, the
POR is inactive per the data sheet. Inside the
region, the POR will assert Reset and will not
release Reset until power is removed and V
DD
reaches VSS. Because the POR is independent of
other Reset circuits (see Figure 9-4 of the data
sheet), activating BOR or using the MCLR input will
not eliminate the problem.
Work around
To resolve this problem, the application must be
designed to assure that V
DD reaches VSS. This is
described as D003 V
POR in Section 12.0
“Electrical Specifications” of the Device Data
Sheet (DS41190F).
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B0).
A9
B0
X
X
A9 B0
X