Datasheet

PIC12F609/615/617/12HV609/615
DS41302D-page 8  2010 Microchip Technology Inc.
FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
GPIO
8
8
8
3
8-Level Stack
64 Bytes and
1K X 14
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR
VSS
Brown-out
Reset
Timer0 Timer1
GP0
GP1
GP2
GP3
GP4
GP5
Analog Comparator
T0CKI
INT
T1CKI
Configuration
Internal
Oscillator
VREF
and Reference
T1G
VDD
Timer2
Block
Shunt Regulator
(PIC12HV615 only)
Analog-To-Digital Converter
AN0 AN1 AN2 AN3 CIN+ CIN0- CIN1- COUT
ECCP
CCP1/P1A P1B P1A* P1B*
Comparator Voltage Reference
Absolute Voltage Reference
* Alternate pin function.
** For the PIC12F617 only.
T1G*
2K X 14**
and
128 Bytes**