Datasheet

PIC12F609/615/617/12HV609/615
DS41302D-page 66  2010 Microchip Technology Inc.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
REGISTER 8-1: T2CON: TIMER 2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 =1:1 Postscaler
0001 =1:2 Postscaler
0010 =1:3 Postscaler
0011 =1:4 Postscaler
0100 =1:5 Postscaler
0101 =1:6 Postscaler
0110 =1:7 Postscaler
0111 =1:8 Postscaler
1000 =1:9 Postscaler
1001 =1:10 Postscaler
1010 =1:11 Postscaler
1011 =1:12 Postscaler
1100 =1:13 Postscaler
1101 =1:14 Postscaler
1110 =1:15 Postscaler
1111 =1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
1x =Prescaler is 16
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE
T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000
PIE1
— ADIE
(1)
CCP1IE
(1)
— CMIE —TMR2IE
(1)
TMR1IE -00- 0-00 -00- 0-00
PIR1
— ADIF
(1)
CCP1IF
(1)
— CMIF —TMR2IF
(1)
TMR1IF -00- 0-00 -00- 0-00
PR2
(1)
Timer2 Module Period Register 1111 1111 1111 1111
TMR2
(1)
Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
T2CON
(1)
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
Note 1: For PIC12F615/617/HV615 only.