Datasheet
2010 Microchip Technology Inc. DS41302D-page 51
PIC12F609/615/617/12HV609/615
5.2.4.6 GP5/T1CKI/P1A
(1, 2)
/OSC1/CLKIN
Figure 5-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a Timer1 clock input
• PWM output, alternate pin
(1, 2)
• a crystal/resonator connection
• a clock input
FIGURE 5-5: BLOCK DIAGRAM OF GP5
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPU
RD
WPU
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
To Timer1
INTOSC
Mode
RD GPIO
INTOSC
Mode
GPPU
OSC2
Note 1: Timer1 LP Oscillator enabled.
2: Set has priority over Reset.
TMR1LPEN
(1)
Oscillator
Circuit
Q1
I/O Pin
Interrupt-on-
Change
S
(2)
R
Q
From other
GP<4:0> pins
Write ‘0’ to GBIF