Datasheet
2010 Microchip Technology Inc. DS41302D-page 49
PIC12F609/615/617/12HV609/615
5.2.4.4 GP3/T1G
(1, 2)
/MCLR/VPP
Figure 5-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
• a Timer1 gate (count enable), alternate pin
(1, 2)
• as Master Clear Reset with weak pull-up
FIGURE 5-3: BLOCK DIAGRAM OF GP3
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
VSS
D
Q
CK
Q
D
EN
Q
Data Bus
RD GPIO
RD
GPIO
WR
IOC
RD
IOC
Reset
MCLRE
RD
TRISIO
VSS
D
EN
Q
MCLRE
VDD
Weak
MCLRE
Q1
Input
Pin
Interrupt-on-
Change
S
(1)
R
Q
From other
Write ‘0’ to GBIF
Note 1: Set has priority over Reset
GP<5:4, 2:0> pins