Datasheet
2010 Microchip Technology Inc. DS41302D-page 17
PIC12F609/615/617/12HV609/615
TABLE 2-4: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116
81h OPTION_REG GPPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19, 116
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116
83h STATUS IRP
(1)
RP1
(1)
RP0 TO PD ZDCC0001 1xxx 18, 116
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116
85h TRISIO
— — TRISIO5 TRISIO4 TRISIO3
(4)
TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116
86h — Unimplemented — —
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
(3)
0000 0000 20, 116
8Ch PIE1
— ADIE CCP1IE —CMIE— TMR2IE TMR1IE -00- 0-00 21, 116
8Dh — Unimplemented — —
8Eh PCON
— — — — — —PORBOR ---- --qq 23, 116
8Fh — Unimplemented — —
90h OSCTUNE
— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116
91h — Unimplemented — —
92h PR2 Timer2 Module Period Register 1111 1111 65, 116
93h APFCON
— — — T1GSEL — — P1BSEL P1ASEL ---0 --00 21, 116
94h — Unimplemented — —
95h WPU
(2)
— —WPU5WPU4— WPU2 WPU1 WPU0 --11 -111 46, 116
96h IOC
— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116
97h — Unimplemented — —
98h PMCON1
(7)
— — — — — WREN WR RD ---- -000 29
99h PMCON2
(7)
Program Memory Control Register 2 (not a physical register). ---- ---- —
9Ah PMADRL
(7)
PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 28
9Bh PMADRH
(7)
— — — — — PMADRH2 PMADRH1 PMADRH0 ---- -000 28
9Ch PMDATL
(7)
PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 28
9Dh PMDATH
(7)
— — Program Memory Data Register High Byte. --00 0000 28
9Eh ADRESL
(5, 6)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 85, 117
9Fh ANSEL
— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 45, 117
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
3: MCLR
and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
4: TRISIO3 always reads as ‘1’ since it is an input only pin.
5: Read only register.
6: PIC12F615/617/HV615 only.
7: PIC12F617 only.