Datasheet
PIC12F609/615/617/12HV609/615
DS41302D-page 16 2010 Microchip Technology Inc.
TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116
81h OPTION_RE
G
GPPU
INTEDG T0CS
T0SE PSA PS2 PS1 PS0 1111 1111 19, 116
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116
83h STATUS IRP
(1)
RP1
(1)
RP0 TO PD ZDCC0001 1xxx 18, 116
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116
85h TRISIO
— — TRISIO5 TRISIO4 TRISIO3
(4)
TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116
86h — Unimplemented — —
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
(3)
0000 0000 20, 116
8Ch PIE1
— — — —CMIE— —TMR1IE---- 0--0 21, 116
8Dh — Unimplemented — —
8Eh PCON
— — — — — —PORBOR ---- --qq 23, 116
8Fh — Unimplemented — —
90h OSCTUNE
— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116
91h — Unimplemented — —
92h — Unimplemented — —
93h — Unimplemented — —
94h — Unimplemented — —
95h WPU
(2)
— —WPU5WPU4— WPU2 WPU1 WPU0 --11 -111 46, 116
96h IOC
— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ANSEL
— — — —ANS3— ANS1 ANS0 ---- 1-11 45, 117
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
3: MCLR
and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
4: TRISIO3 always reads as ‘1’ since it is an input only pin.