Datasheet

PIC12F609/615/617/12HV609/615
DS41302D-page 122  2010 Microchip Technology Inc.
12.6.2 WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst-
case conditions (i.e., V
DD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT time out occurs.
FIGURE 12-2: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
TABLE 12-8: WDT STATUS
Conditions WDT
WDTE = 0
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
OPTION_REG
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
CONFIG
IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of all Configuration Word register bits.
T0CKI
T0SE
pin
CLKOUT
TMR0
Watchdog
Timer
WDT
Time-Out
PS<2:0>
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
0
1
0
1
0
1
SYNC 2
Cycles
8
8
8-bit
Prescaler
0
1
(= FOSC/4)
PSA
PSA
PSA
3