Datasheet

PIC12F609/615/617/12HV609/615
DS41302D-page 112  2010 Microchip Technology Inc.
12.3.4 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word register select one of three BOR modes. One
mode has been added to allow control of the BOR
enable for lower current during Sleep. By selecting
BOREN<1:0> = 10, the BOR is automatically disabled
in Sleep to conserve power and enabled on wake-up.
See Register 12-1 for the Configuration Word
definition.
A brown-out occurs when V
DD falls below VBOR for
greater than parameter T
BOR (see Section 16.0
“Electrical Specifications”). The brown-out condition
will reset the device. This will occur regardless of VDD
slew rate. A Brown-out Reset may not occur if VDD falls
below V
BOR for less than parameter TBOR.
On any Reset (Power-on, Brown-out Reset, Watchdog
timer, etc.), the chip will remain in Reset until VDD rises
above V
BOR (see Figure 12-3). If enabled, the Power-
up Timer will be invoked by the Reset and keep the chip
in Reset an additional 64 ms.
If V
DD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
FIGURE 12-3: BROWN-OUT SITUATIONS
Note: The Power-up Timer is enabled by the
PWRTE
bit in the Configuration Word
register.
64 ms
(1)
VBOR
V
DD
Internal
Reset
VBOR
V
DD
Internal
Reset
64 ms
(1)
< 64 ms
64 ms
(1)
VBOR
V
DD
Internal
Reset
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.