PIC12F609/615/617 PIC12HV609/615 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC12F609/615/617/12HV609/615 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers High-Performance RISC CPU: Peripheral Features: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes • Shunt Voltage Regulator (PIC12HV609/615 only): - 5 volt regulation - 4 mA to 50 mA shunt range • 5 I/O Pins and
PIC12F609/615/617/12HV609/615 Device Program Memory Data Memory Flash (words) SRAM (bytes) Self Read/ Self Write PIC12HV615 1024 64 — — — — PIC12F617 2048 128 YES PIC12F609 1024 64 PIC12HV609 1024 64 PIC12F615 1024 64 I/O 10-bit A/D Comparators ECCP (ch) Timers 8/16-bit Voltage Range 5 0 1 2.0V-5.5V 0 1 — — 1/1 5 1/1 2.0V-user defined 5 4 1 YES 2/1 2.0V-5.5V 5 4 1 YES 2/1 2.0V-user defined 5 4 1 YES 2/1 2.0V-5.
PIC12F609/615/617/12HV609/615 8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN) VDD 1 8 GP5/T1CKI/P1A*/OSC1/CLKIN 2 GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT 3 PIC12F615/ 7 617/HV615 6 GP3/T1G*/MCLR/VPP 4 5 * VSS GP0/AN0/CIN+/P1B/ICSPDAT GP1/AN1/CIN0-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/P1A Alternate pin function.
PIC12F609/615/617/12HV609/615 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................ 11 3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only)..............
PIC12F609/615/617/12HV609/615 1.0 DEVICE OVERVIEW Block Diagrams and pinout descriptions of the devices are as follows: The PIC12F609/615/617/12HV609/615 devices are covered by this data sheet. They are available in 8-pin PDIP, SOIC, MSOP and DFN packages.
PIC12F609/615/617/12HV609/615 FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM INT Configuration 13 Flash 1K X 14 and 2K X 14** Program Memory Program Bus 8 Data Bus GPIO Program Counter GP0 GP1 GP2 GP3 GP4 GP5 RAM 64 Bytes and 128 Bytes** File Registers 8-Level Stack (13-Bit) 14 RAM Addr 9 Addr MUX Instruction Reg 7 Direct Addr Indirect Addr 8 FSR Reg STATUS Reg 8 3 Power-up Timer OSC1/CLKIN Instruction Decode & Control Oscillator Start-up Timer Timing Generation Watchdog Timer Power-o
PIC12F609/615/617/12HV609/615 TABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION Name Function Input Type Output Type GP0/CIN+/ICSPDAT GP0 TTL CMOS CIN+ AN — ICSPDAT ST CMOS GP1 TTL CMOS CIN0- AN — Comparator inverting input Serial Programming Clock GP1/CIN0-/ICSPCLK ICSPCLK ST — GP2 ST CMOS T0CKI ST — GP2/T0CKI/INT/COUT INT ST — COUT — CMOS General purpose I/O with prog.
PIC12F609/615/617/12HV609/615 TABLE 1-2: PIC12F615/617/HV615 PINOUT DESCRIPTION Name GP0/AN0/CIN+/P1B/ICSPDAT GP1/AN1/CIN0-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A GP3/T1G*/MCLR/VPP GP4/AN3/CIN1-/T1G/P1B*/OSC2/ CLKOUT GP5/T1CKI/P1A*/OSC1/CLKIN Function Input Type Output Type GP0 TTL CMOS Description General purpose I/O with prog.
PIC12F609/615/617/12HV609/615 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization FIGURE 2-2: The PIC12F609/615/617/12HV609/615 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h03FFh) for the PIC12F609/615/12HV609/615 is physically implemented. For the PIC12F617, the first 2K x 14 (0000h-07FFh) is physically implemented.
PIC12F609/615/617/12HV609/615 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the PIC12F609/615/12HV609/615, and as 128 x 8 in the PIC12F617. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 FIGURE 2-3: DATA MEMORY MAP OF THE PIC12F609/HV609 File Address File Address Indirect Addr.(1) 00h Indirect Addr.
PIC12F609/615/617/12HV609/615 FIGURE 2-4: DATA MEMORY MAP OF THE PIC12F615/617/HV615 File Address File Address Indirect Addr.(1) 00h Indirect Addr.
PIC12F609/615/617/12HV609/615 TABLE 2-1: Addr Name PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 115 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 115 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 115 03h STATUS 0001 1xxx 18, 115 xxxx xxxx 25, 115
PIC12F609/615/617/12HV609/615 TABLE 2-2: Addr Name PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 116 02h PCL Program Counter’s (PC) Least Significant Byte 03h STATUS 04h FSR 05h GPIO IRP(1) RP1(1) RP0 0000 0000 25, 1
PIC12F609/615/617/12HV609/615 TABLE 2-3: Addr Name PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF 81h OPTION_RE G Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL 83h STATUS 84h FSR 85h TRISIO GPPU INTEDG T0CS T0SE PS2 PS1 PS0 TO PD Z DC C 0001 1xxx 18, 116 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 11
PIC12F609/615/617/12HV609/615 TABLE 2-4: Addr Name PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL 83h STATUS GPPU INTEDG T0CS T0SE xxxx xxxx 25, 116 PSA PS2 PS1 PS0 1111 1111 19, 116 TO PD Z DC C 0001 1xxx 18, 116 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TR
PIC12F609/615/617/12HV609/615 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (RAM) It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the Section 14.0 “Instruction Set Summary”.
PIC12F609/615/617/12HV609/615 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External GP2/INT interrupt Timer0 Weak pull-ups on GPIO REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 6.1.3 “Software Programmable Prescaler”.
PIC12F609/615/617/12HV609/615 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO change and external GP2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register.
PIC12F609/615/617/12HV609/615 2.2.2.4 PIE1 Register The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC12F609/615/617/12HV609/615 2.2.2.5 PIR1 Register The PIR1 register contains the Peripheral Interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: U-0 Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC12F609/615/617/12HV609/615 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-6.
PIC12F609/615/617/12HV609/615 2.2.2.7 APFCON Register (PIC12F615/617/HV615 only) The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. For this device, the P1A, P1B and Timer1 Gate functions can be moved between different pins. The APFCON register bits are shown in Register 2-7.
PIC12F609/615/617/12HV609/615 2.3 2.3.2 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC12F609/615/617/12HV609/615 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615 Direct Addressing RP1(1) RP0 6 Bank Select From Opcode Indirect Addressing IRP(1) 0 7 Bank Select Location Select 00 01 10 File Select Register 0 Location Select 11 00h 180h NOT USED(2) Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figure 2-3. Note 1: 2: The RP1 and IRP bits are reserved; always maintain these bits clear.
PIC12F609/615/617/12HV609/615 3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY) The Flash program memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5).
PIC12F609/615/617/12HV609/615 REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown PMDATL<7:0>: 8 Least Significant Address bits to Write or Read from Program Memory REGISTER 3-2: PMADRL: PROGRAM MEMO
PIC12F609/615/617/12HV609/615 REGISTER 3-5: U-1 — PMCON1 – PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h) U-0 — U-0 — U-0 — U-0 — R/W-0 WREN R/S-0 WR bit 7 R/S-0 RD bit 0 bit 7 Unimplemented: Read as ‘1’ bit 6-3 Unimplemented: Read as ‘0’ bit 2 WREN: Program Memory Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle to program memory. (The bit is cleared by hardware when write is complete.
PIC12F609/615/617/12HV609/615 3.3 Reading the Flash Program Memory To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored.
PIC12F609/615/617/12HV609/615 FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Flash ADDR Q2 Q3 Q4 PC Flash DATA Q1 Q2 Q4 PC + 1 INSTR (PC) INSTR (PC - 1) Executed here Q3 Q1 Q2 Q3 Q4 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD Executed here Q1 Q2 Q3 PC+3 PC +3 PMDATH,PMDATL INSTR (PC + 1) Executed here Q4 Q1 Q2 Q3 Q4 NOP Executed here Q2 Q3 Q4 PC + 5 PC + 4 INSTR (PC + 3) Q1 INSTR (PC + 4) INSTR (PC + 3) Executed here INSTR (PC + 4) Executed here RD bit
PIC12F609/615/617/12HV609/615 3.4 Writing the Flash Program Memory A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory. Flash program memory must be written in four-word blocks. See Figure 3-2 and Figure 3-3 for more details. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where PMADRL<1:0> = 00. All block writes to program memory are done as 16-word erase by fourword write operations.
PIC12F609/615/617/12HV609/615 FIGURE 3-2: BLOCK WRITES TO 2K FLASH PROGRAM MEMORY 7 5 0 0 7 PMDATH If at a new row sixteen words of Flash are erased, then four buffers are transferred to Flash automatically after this word is written PMDATL 6 8 14 14 First word of block to be written 14 PMADRL<1:0> = 00 PMADRL<1:0> = 10 PMADRL<1:0> = 01 Buffer Register Buffer Register 14 PMADRL<1:0> = 11 Buffer Register Buffer Register Program Memory FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXE
PIC12F609/615/617/12HV609/615 An example of the complete four-word write sequence is shown in Example 3-2. The initial address is loaded into the PMADRH and PMADRL register pair; the eight words of data are loaded using indirect addressing.
PIC12F609/615/617/12HV609/615 TABLE 3-1: Name PMCON1 SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — — — — WREN WR RD ---- -000 ---- -000 ---- ---- ---- ---- PMCON2 Program Memory Control Register 2 (not a physical register) PMADRL PMADRL7 PMADRL6 PMADRL5 PMADRH PMDATL PMDATH Legend: — PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 0000 0000 — — — PMADRH2 PMADRH1 PMADRH0 -
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 36 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 4.0 OSCILLATOR MODULE The Oscillator module can be configured in one of eight clock modes. 4.1 Overview 3. 4. 5. The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the Oscillator module.
PIC12F609/615/617/12HV609/615 4.2 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. • Internal clock sources are contained internally within the Oscillator module.
PIC12F609/615/617/12HV609/615 4.3.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.
PIC12F609/615/617/12HV609/615 4.3.4 EXTERNAL RC MODES 4.4 Internal Clock Modes The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. The Oscillator module provides a selectable system clock source of either 4 MHz or 8 MHz.
PIC12F609/615/617/12HV609/615 4.4.1.1 OSCTUNE Register The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-1). REGISTER 4-1: When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 42 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 5.0 I/O PORT There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 5.1 GPIO and the TRISIO Registers GPIO is a 6-bit wide port with 5 bidirectional and 1 inputonly pin. The corresponding data direction register is TRISIO (Register 5-2).
PIC12F609/615/617/12HV609/615 REGISTER 5-2: TRISIO: GPIO TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISIO<5:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output
PIC12F609/615/617/12HV609/615 REGISTER 5-3: ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609) U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 — — — — ANS3 — ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 ANS3: Analog Select Between Analog or Digital Function on Pin GP4 1 = Analog input. Pin is assigned as analog input(1).
PIC12F609/615/617/12HV609/615 REGISTER 5-5: WPU: WEAK PULL-UP GPIO REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPU5 WPU4 — WPU2 WPU1 WPU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 WPU<3>: Weak Pull-up Register bit(3) bit 2-0 WPU<2:0>: Weak
PIC12F609/615/617/12HV609/615 5.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. GP0/AN0(1)/CIN+/P1B(1)/ICSPDAT 5.2.4.1 Figure 5-1 shows the diagram for this pin.
PIC12F609/615/617/12HV609/615 GP2/AN2(1)/T0CKI/INT/COUT/ CCP1(1)/P1A(1) 5.2.4.3 Note 1: Figure 5-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: • • • • • • • PIC12F615/617/HV615 only.
PIC12F609/615/617/12HV609/615 5.2.4.4 GP3/T1G(1, 2)/MCLR/VPP Figure 5-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • a Timer1 gate (count enable), alternate pin(1, 2) • as Master Clear Reset with weak pull-up Note 1: Alternate pin function. 2: PIC12F615/617/HV615 only.
PIC12F609/615/617/12HV609/615 5.2.4.5 GP4/AN3(2)/CIN1-/T1G/ P1B(1, 2)/OSC2/CLKOUT Figure 5-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • • • • Note 1: Alternate pin function. a general purpose I/O an analog input for the ADC(2) Comparator inverting input a Timer1 gate (count enable) FIGURE 5-4: • PWM output, alternate pin(1, 2) • a crystal/resonator connection • a clock output 2: PIC12F615/617/HV615 only.
PIC12F609/615/617/12HV609/615 5.2.4.6 GP5/T1CKI/P1A(1, 2)/OSC1/CLKIN Note 1: Alternate pin function. Figure 5-5 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: • • • • • 2: PIC12F615/617/HV615 only.
PIC12F609/615/617/12HV609/615 TABLE 5-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -000 1111 — ADCS2(1) ADCS1(1) ADCS0(1) ANS3 ANS2(1) ANS1 ANS0 -000 1111 CMCON0 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -0-0 0000 -0-0 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 ANSEL IOC GPPU INTEDG T
PIC12F609/615/617/12HV609/615 6.0 TIMER0 MODULE 6.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 6.1.
PIC12F609/615/617/12HV609/615 6.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256.
PIC12F609/615/617/12HV609/615 REGISTER 6-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register bit 6 INTEDG: I
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 56 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 7.
PIC12F609/615/617/12HV609/615 FIGURE 7-1: TIMER1 BLOCK DIAGRAM TMR1GE T1GINV TMR1ON Set flag bit TMR1IF on Overflow To Comparator Module Timer1 Clock TMR1(2) TMR1H TMR1L 0 EN Synchronized clock input 1 Oscillator (1) T1SYNC OSC1/T1CKI 1 Prescaler 1, 2, 4, 8 0 OSC2/T1G Synchronize(3) det 2 T1CKPS<1:0> TMR1CS 0 INTOSC Without CLKOUT T1OSCEN FOSC 1 1 1 FOSC/4 Internal Clock 0 COUT 0 T1GSEL(2) T1GSS T1ACS GP3/T1G(4, 5) Note 1: 2: 3: 4: 5: ST Buffer is low power type when using LP os
PIC12F609/615/617/12HV609/615 7.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 7.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI.
PIC12F609/615/617/12HV609/615 7.6 Timer1 Gate Timer1 gate source is software configurable to be the T1G pin (or the alternate T1G pin) or the output of the Comparator. This allows the device to directly time external events using T1G or analog events using the Comparator. See the CMCON1 Register (Register 9-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications.
PIC12F609/615/617/12HV609/615 7.10 ECCP Special Event Trigger (PIC12F615/617/HV615 only) If a ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to generate a ECCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1. Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger.
PIC12F609/615/617/12HV609/615 7.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 7-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC12F609/615/617/12HV609/615 TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 APFCON(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — — T1GSEL — — P1BSEL P1ASEL ---0 --00 ---0 --00 CMCON0 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -0-0 0000 -0-0 CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 ---0 0-10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x PIE1 — ADIE(1) CCP1IE(1)
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 64 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 8.0 TIMER2 MODULE (PIC12F615/617/HV615 ONLY) The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh.
PIC12F609/615/617/12HV609/615 REGISTER 8-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011
PIC12F609/615/617/12HV609/615 9.0 COMPARATOR MODULE than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The comparator can be used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes.
PIC12F609/615/617/12HV609/615 9.2 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 9-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC12F609/615/617/12HV609/615 9.3 Comparator Control The comparator has two control and Configuration registers: CMCON0 and CMCON1. The CMCON1 register is used for controlling the interaction with Timer1 and simultaneously reading the comparator output. The CMCON0 register (Register 9-1) contain the control and Status bits for the following: • • • • • Enable Input selection Reference selection Output selection Output polarity 9.3.
PIC12F609/615/617/12HV609/615 9.5 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 9-4 and Figure 9-5). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset.
PIC12F609/615/617/12HV609/615 9.6 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 16.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by clearing the CMON bit of the CMCON0 register.
PIC12F609/615/617/12HV609/615 REGISTER 9-1: CMCON0: COMPARATOR CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 CMON COUT CMOE CMPOL — CMR — CMCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CMON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COUT: Comparator Output bit If C1POL = 1 (inverted polarity): COUT = 0 when CMVIN+ > CM
PIC12F609/615/617/12HV609/615 9.8 Comparator Gating Timer1 9.9 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator. This requires that Timer1 is on and gating is enabled. See Section 7.0 “Timer1 Module with Gate Control” for details.
PIC12F609/615/617/12HV609/615 9.10 Comparator Voltage Reference 9.10.3 OUTPUT CLAMPED TO VSS The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: • • • • • This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current.
PIC12F609/615/617/12HV609/615 FIGURE 9-6: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD VRR 8R CMVREN Analog MUX 15 CVREF(1) To Comparators and ADC Module 0 VR<3:0>(1) 4 FVREN Sleep HFINTOSC enable FixedRef To Comparators and ADC Module Note 1: 0.6V EN Fixed Voltage Reference Care should be taken to ensure CVREF remains within the comparator common mode input range. See Section 16.0 “Electrical Specifications” for more detail. 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 REGISTER 9-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMVREN — VRR FVREN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown CMVREN: Comparator Voltage Reference Enable bit(1, 2) 1 = CVREF circuit powered on and routed to CVREF input of the Comparator 0 = 0.
PIC12F609/615/617/12HV609/615 9.11 Comparator Hysteresis Each comparator has built-in hysteresis that is user enabled by setting the CMHYS bit of the CMCON1 register. The hysteresis feature can help filter noise and reduce multiple comparator output transitions when the output is changing state. FIGURE 9-7: Figure 9-7 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis.
PIC12F609/615/617/12HV609/615 TABLE 9-2: Name ANSEL CMCON0 SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Value on POR, BOR Bit 0 Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — ADCS2(1) ADCS1(1) ADCS0(1) ANS3 ANS2(1) ANS1 ANS0 -000 1111 -000 1111 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -000 0000 -000 CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC 0000 0000 0000 0000 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF G
PIC12F609/615/617/12HV609/615 10.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC12F615/617/HV615 ONLY) Note: The ADRESL and ADRESH registers are Read Only. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC12F609/615/617/12HV609/615 10.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 10.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits.
PIC12F609/615/617/12HV609/615 TABLE 10-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0> 20 MHz FOSC/2 000 100 ns FOSC/4 100 200 ns(2) 001 400 ns (2) 800 ns (2) FOSC/8 FOSC/16 101 FOSC/32 010 1.6 s FOSC/64 110 3.2 s FRC x11 2-6 s(1,4) Legend: Note 1: 2: 3: 4: 8 MHz (2) 4 MHz 1 MHz (2) 2.0 s 1.0 s(2) 4.0 s 2.0 s 8.0 s(3) 2.0 s 4.0 s 16.0 s(3) 4.0 s 8.
PIC12F609/615/617/12HV609/615 10.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 10-4 shows the two output formats. FIGURE 10-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result Unimplemented: Read as ‘0’ MSB (ADFM = 1) bit 7 LSB bit 0 Unimplemented: Read as ‘0’ 10.2 10.2.
PIC12F609/615/617/12HV609/615 10.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC12F609/615/617/12HV609/615 10.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC12F609/615/617/12HV609/615 REGISTER 10-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 10-3: ADRESL: ADC RESULT RE
PIC12F609/615/617/12HV609/615 10.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 10-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 10-4.
PIC12F609/615/617/12HV609/615 FIGURE 10-4: ANALOG INPUT MODEL VDD ANx Rs CPIN 5 pF VA VT = 0.6V VT = 0.
PIC12F609/615/617/12HV609/615 TABLE 10-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 ADCON0(1) ADFM VCFG — ADCS2(1) ANSEL (1,2) ADRESH Bit 6 Bit 5 Bit 4 Bit 3 — CHS2 ADCS1(1) ADCS0(1) Value on POR, BOR Value on all other Resets Bit 2 Bit 1 Bit 0 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000 ANS3 ANS2(1) ANS1 ANS0 -000 1111 -000 1111 A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL(1,2) A/D Result Register Low Byte xxxx xxxx uuuu uuuu — — GP5 GP4 GP3 GP2 G
PIC12F609/615/617/12HV609/615 11.0 ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTOSHUTDOWN AND DEAD BAND) MODULE (PIC12F615/617/ HV615 ONLY) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event.The Compare mode allows the user to trigger an external REGISTER 11-1: event when a predetermined amount of time has expired.
PIC12F609/615/617/12HV609/615 11.1 11.1.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software.
PIC12F609/615/617/12HV609/615 TABLE 11-2: Name CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 Bit 0 Value on POR, BOR Value on all other Resets CCP1M0 0-00 0000 0-00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(
PIC12F609/615/617/12HV609/615 11.2 11.2.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • • • • • Toggle the CCP1 output. Set the CCP1 output. Clear the CCP1 output. Generate a Special Event Trigger. Generate a Software Interrupt. All Compare modes can generate an interrupt.
PIC12F609/615/617/12HV609/615 TABLE 11-3: Name CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 Bit 0 Value on POR, BOR Value on all other Resets CCP1M0 0-00 0000 0-00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(
PIC12F609/615/617/12HV609/615 11.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • • • • PR2 T2CON CCPR1L CCP1CON FIGURE 11-4: CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin.
PIC12F609/615/617/12HV609/615 11.3.1 PWM PERIOD EQUATION 11-2: The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 11-1.
PIC12F609/615/617/12HV609/615 11.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 11.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 4.
PIC12F609/615/617/12HV609/615 11.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. The Enhanced PWM Mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: Table 11-6 shows the pin assignments for each Enhanced PWM mode.
PIC12F609/615/617/12HV609/615 FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal P1M<1:0> PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active Relationships: P1B Inactive • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) P1C Inactive • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is pro
PIC12F609/615/617/12HV609/615 11.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 11-8). This mode can be used for Half-Bridge applications, as shown in Figure 11-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
PIC12F609/615/617/12HV609/615 11.4.2 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s).
PIC12F609/615/617/12HV609/615 11.4.4 ENHANCED PWM AUTOSHUTDOWN MODE A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. Refer to Figure 1. The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state.
PIC12F609/615/617/12HV609/615 REGISTER 11-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs
PIC12F609/615/617/12HV609/615 FIGURE 11-11: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) Shutdown Event ECCPASE bit PWM Activity PWM Period ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes Start of PWM Period 11.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register.
PIC12F609/615/617/12HV609/615 11.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 11-13: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC12F609/615/617/12HV609/615 REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restart
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 106 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 12.0 SPECIAL FEATURES OF THE CPU The PIC12F609/615/617/12HV609/615 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection.
PIC12F609/615/617/12HV609/615 REGISTER 12-1: U-1 — U-1 — U-1 — CONFIG: CONFIGURATION WORD REGISTER (ADDRESS: 2007h) FOR PIC12F609/615/HV609/615 ONLY U-1 — R/P-1 BOREN1 R/P-1 (1) BOREN0 R/P-1 (1) R/P-1 IOSCFS CP (2) R/P-1 MCLRE (3) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 13 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13-10
PIC12F609/615/617/12HV609/615 REGISTER 12-2: U-1 U-1 — — R/P-1 CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) FOR PIC12F617 ONLY R/P-1 R/P-1 R/P-1 R/P-1 WRT1 WRT0 BOREN1 BOREN0 IOSCFS R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE R/P-1 R/P-1 R/P-1 R/P-1 WDTE FOSC2 F0SC1 F0SC0 bit 13 bit 0 bit 13-12 Unimplemented: Read as ‘1’ bit 11-10 WRT<1:0>: Flash Program Memory Self Write Enable bits 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to 7FFh may be modified by PMCON1 control 01
PIC12F609/615/617/12HV609/615 12.2 Calibration Bits The 8 MHz internal oscillator is factory calibrated. These calibration values are stored in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the Memory Programming Specification (DS41204) and thus, does not require reprogramming. 12.
PIC12F609/615/617/12HV609/615 12.3.1 POWER-ON RESET (POR) The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 16.0 “Electrical Specifications” for details.
PIC12F609/615/617/12HV609/615 12.3.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 12-3). If enabled, the Powerup Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms. The BOREN0 and BOREN1 bits in the Configuration Word register select one of three BOR modes. One mode has been added to allow control of the BOR enable for lower current during Sleep.
PIC12F609/615/617/12HV609/615 12.3.5 TIME-OUT SEQUENCE 12.3.6 On power-up, the time-out sequence is as follows: The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred last. • PWRT time-out is invoked after POR has expired. • OST is activated after the PWRT time-out has expired. Bit 0 is BOR (Brown-out). BOR is unknown on Poweron Reset.
PIC12F609/615/617/12HV609/615 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 12-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41302D-page 114 2010 Microchip Technology I
PIC12F609/615/617/12HV609/615 TABLE 12-4: Register W INDF TMR0 INITIALIZATION CONDITION FOR REGISTERS (PIC12F609/HV609) Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx
PIC12F609/615/617/12HV609/615 TABLE 12-5: Register INITIALIZATION CONDITION FOR REGISTERS (PIC12F615/617/HV615) Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) W INDF TMR0 Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xx
PIC12F609/615/617/12HV609/615 TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)(PIC12F615/617/HV615) Register PMADRH(6) Address Power-on Reset MCLR Reset WDT Reset (Continued) Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) 9Bh ---- -000 ---- -000 ---- -uuu (6) 9Ch 0000 0000 0000 0000 uuuu uuuu PMDATH(6) 9Dh --00 0000 --00 0000 --uu uuuu ADRESL(1) 9Eh xxxx xxxx uuuu uuuu uuuu uuuu 9Fh -000 1111 -000 1111 -
PIC12F609/615/617/12HV609/615 12.
PIC12F609/615/617/12HV609/615 12.4.2 TIMER0 INTERRUPT 12.4.3 An overflow (FFh 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 6.0 “Timer0 Module” for operation of the Timer0 module. An input change on GPIO sets the GPIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the GPIE bit of the INTCON register.
PIC12F609/615/617/12HV609/615 FIGURE 12-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF flag (INTCON reg.) Interrupt Latency (2) (5) GIE bit (INTCON reg.
PIC12F609/615/617/12HV609/615 12.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure 2-3). These 16 locations are common to all banks and do not require banking.
PIC12F609/615/617/12HV609/615 12.6.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worstcase conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT time out occurs.
PIC12F609/615/617/12HV609/615 12.7 Power-Down Mode (Sleep) The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance).
PIC12F609/615/617/12HV609/615 FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON reg.) Interrupt Latency (3) GIE bit (INTCON reg.) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 12.
PIC12F609/615/617/12HV609/615 12.10 In-Circuit Serial Programming™ 12.11 In-Circuit Debugger ThePIC12F609/615/617/12HV609/615 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five connections for: Since in-circuit debugging requires access to three pins, MPLAB® ICD 2 development with an 14-pin device is not practical.
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 126 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 13.0 VOLTAGE REGULATOR The PIC12HV609/HV615 devices include a permanent internal 5 volt (nominal) shunt regulator in parallel with the VDD pin. This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All external devices connected directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). 13.
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 128 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 14.
PIC12F609/615/617/12HV609/615 TABLE 14-2: PIC12F609/615/617/12HV609/615 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Ski
PIC12F609/615/617/12HV609/615 14.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 127 0b7 Operation: 0 (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC12F609/615/617/12HV609/615 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 f 127 0b<7 Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC12F609/615/617/12HV609/615 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC12F609/615/617/12HV609/615 MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] MOVF f,d MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 f 127 Operation: (W) (f) f Operation: (f) (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself.
PIC12F609/615/617/12HV609/615 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: TOS PC, 1 GIE Operation: k (W); TOS PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC12F609/615/617/12HV609/615 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC12F609/615/617/12HV609/615 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Operation: (W) .XOR. (f) destination) Status Affected: C, DC, Z Status Affected: Z Description: Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 138 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 15.
PIC12F609/615/617/12HV609/615 15.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
PIC12F609/615/617/12HV609/615 15.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC12F609/615/617/12HV609/615 15.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 15.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC12F609/615/617/12HV609/615 16.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ..............................................................................
PIC12F609/615/617/12HV609/615 FIGURE 16-1: PIC12F609/615/617 VOLTAGE-FREQUENCY GRAPH, -40°C TA +125°C 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 16-2: PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH, -40°C TA +125°C 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC12F609/615/617/12HV609/615 16.1 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Min Typ† Max Units 2.0 — 5.5 V Sym VDD D001 Characteristic Conditions Supply Voltage PIC12F609/615/617 (2) FOSC < = 4 MHz D001 PIC12HV609/615 2.
PIC12F609/615/617/12HV609/615 16.2 DC Characteristics: PIC12F609/615/617-I (Industrial) PIC12F609/615/617-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param No. D010 Conditions Device Characteristics PIC12F609/615/617 D011* D012 D013* D014 D016* D017 D018 D019 Note 1: 2: 3: Typ† Max Units Note VDD Supply Current (IDD) * † Min (1, 2) — 13 25 A 2.
PIC12F609/615/617/12HV609/615 16.3 DC Characteristics: PIC12HV609/615-I (Industrial) PIC12HV609/615-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param No. D010 Conditions Device Characteristics Min Typ† Max Units — 160 230 A 2.0 — 240 310 A 3.0 — 280 400 A 4.5 — 270 380 A 2.
PIC12F609/615/617/12HV609/615 16.4 DC Characteristics: PIC12F609/615/617 - I (Industrial) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Conditions Device Characteristics Min Typ† Max Units Note VDD 0.9 A 2.0 0.15 1.2 A 3.0 0.35 1.5 A 5.0 150 500 nA 3.0 -40°C TA +25°C for industrial — 0.5 1.5 A 2.0 WDT Current(1) — 2.5 4.0 A 3.
PIC12F609/615/617/12HV609/615 16.5 DC Characteristics: PIC12F609/615/617 - E (Extended) DC CHARACTERISTICS Param No. D020E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2) PIC12F609/615/617 D021E D022E D023E D024E D025E* D026E D027E Min Typ† Max Units VDD Note WDT, BOR, Comparator, VREF and T1OSC disabled — 0.05 4.0 A 2.0 — 0.15 5.0 A 3.0 — 0.35 8.
PIC12F609/615/617/12HV609/615 16.6 DC Characteristics: PIC12HV609/615 - I (Industrial) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Conditions Device Characteristics Min Typ† Max Units Power-down Base Current (IPD)(2,3) — 135 200 A 2.0 — 210 280 A 3.0 PIC12HV609/615 — 260 350 A 4.5 — 135 200 A 2.0 — 210 285 A 3.0 Note VDD D021 — 265 360 A 4.
PIC12F609/615/617/12HV609/615 16.7 DC Characteristics: PIC12HV609/615-E (Extended) DC CHARACTERISTICS Param No. D020E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C for extended Conditions Device Characteristics Min Typ† Max Units VDD Power-down Base Current (IPD)(2,3) PIC12HV609/615 D021E — 135 200 A 2.0 — 210 280 A 3.0 — 260 350 A 4.5 — 135 200 A 2.0 — 210 285 A 3.0 — 265 360 A 4.5 D022E — 215 285 A 3.
PIC12F609/615/617/12HV609/615 16.8 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Vss Vss Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 2.0V VDD 4.5V Vss — 0.2 VDD V 2.0V VDD 5.5V 0.
PIC12F609/615/617/12HV609/615 16.8 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param No.
PIC12F609/615/617/12HV609/615 16.9 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym Characteristic Typ Units 84.6* 149.5* 211* 60* 44* 41.2* 39.9* 39* 9* 3.
PIC12F609/615/617/12HV609/615 16.10 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC12F609/615/617/12HV609/615 16.11 AC Characteristics: PIC12F609/615/617/12HV609/615 (Industrial, Extended) FIGURE 16-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 16-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No.
PIC12F609/615/617/12HV609/615 TABLE 16-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic OS06 TWARM Internal Oscillator Switch when running(3) OS07 INTOSC Internal Calibrated INTOSC Frequency(2) (4MHz) OS08 INTOSC OS10* Internal Calibrated INTOSC Frequency(2) (8MHz) TIOSC ST INTOSC Oscillator Wakeup from Sleep Start-up Time * † Note 1: 2: 3: Freq.
PIC12F609/615/617/12HV609/615 FIGURE 16-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 16-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No.
PIC12F609/615/617/12HV609/615 FIGURE 16-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: FIGURE 16-7: Asserted low.
PIC12F609/615/617/12HV609/615 TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No.
PIC12F609/615/617/12HV609/615 FIGURE 16-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No.
PIC12F609/615/617/12HV609/615 FIGURE 16-9: PIC12F615/617/HV615 CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: TABLE 16-6: Refer to Figure 16-3 for load conditions. PIC12F615/617/HV615 CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. CC01* CC02* CC03* Sym TccL TccH TccP Characteristic CCP1 Input Low Time CCP1 Input High Time Min Typ† Max Units No Prescaler 0.
PIC12F609/615/617/12HV609/615 TABLE 16-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No.
PIC12F609/615/617/12HV609/615 TABLE 16-11: PIC12F615/617/HV615 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param Sym No. Characteristic Min Typ† Max Units Conditions AD01 NR Resolution — — 10 bits AD02 EIL Integral Error — — 1 LSb VREF = 5.12V(5) AD03 EDL Differential Error — — 1 LSb No missing codes to 10 bits VREF = 5.12V(5) AD04 EOFF Offset Error — +1.5 +2.0 LSb VREF = 5.
PIC12F609/615/617/12HV609/615 TABLE 16-12: PIC12F615/617/HV615 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym Characteristic A/D Clock Period AD130* TAD A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min Typ† 1.6 — 9.0 s TOSC-based, VREF 3.0V 3.0 — 9.0 s TOSC-based, VREF full range(3) 3.0 6.0 9.0 s ADCS<1:0> = 11 (ADRC mode) At VDD = 2.
PIC12F609/615/617/12HV609/615 FIGURE 16-11: PIC12F615/617/HV615 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample Note 1: AD132 Sampling Stopped If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS41302D-page 166 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 16.12 High Temperature Operation This section outlines the specifications for the PIC12F615 device operating in a temperature range between -40°C and 150°C.(4) The specifications between -40°C and 150°C(4) are identical to those shown in DS41288 and DS80329. Note 1: Writes are not allowed for Program Memory above 125°C. Flash 2: All AC timing specifications are increased by 30%. This derating factor will include parameters such as TPWRT.
PIC12F609/615/617/12HV609/615 TABLE 16-14: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC12F615-H (High Temp.) Param No. Device Characteristics Condition Units A D011 A D012 58 2.0 19 67 3.0 — 32 92 5.0 — 135 316 2.0 — 185 400 3.0 — 300 537 5.0 495 2.0 360 680 3.0 — 0.660 1.20 5.0 — 75 158 2.0 — 155 338 3.0 — 345 792 5.0 A — 185 357 2.0 — 325 625 3.0 mA — 0.665 1.30 5.0 — 245 476 2.0 — 360 672 3.0 — 620 1.10 5.
PIC12F609/615/617/12HV609/615 TABLE 16-15: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC12F615-H (High Temp.) Param No. D020E Condition Device Characteristics Units Power Down Base Current A A A D023E A A D024E A D025E A D026E A D027E Typ Max VDD D021E D022E Min A — 0.05 12 2.0 — 0.15 13 3.0 — 0.35 14 5.0 — 0.5 20 2.0 — 2.5 25 3.0 — 9.5 36 5.0 — 5.0 28 3.0 — 6.0 36 5.0 — 105 195 2.0 — 110 210 3.0 — 116 220 5.0 — 50 105 2.
PIC12F609/615/617/12HV609/615 TABLE 16-18: OSCILLATOR PARAMETERS FOR PIC12F615-H (High Temp.) Param No. OS08 Note 1: Sym Characteristic INTOSC Int. Calibrated INTOSC Freq.(1) Frequency Tolerance Units Min Typ Max Conditions ±10% MHz 7.2 8.0 8.8 2.0V VDD 5.5V -40°C TA 150°C To ensure these oscillator frequency tolerances, Vdd and Vss must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended.
PIC12F609/615/617/12HV609/615 17.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC12F609/615/617/12HV609/615 FIGURE 17-3: PIC12F609/615/617 IDD EC (4 MHz) vs. VDD 1200 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1000 Maximum IDD EC (µA) 800 Typical 600 400 200 0 2 1 FIGURE 17-4: 3 VDD (V) 4 6 5 PIC12F609/615/617 IDD XT (1 MHz) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-6: PIC12F609/615/617 IDD INTOSC (4 MHz) vs. VDD 900 Maximum 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) IDD INTOSC (µA) 700 Typical 600 500 400 300 200 100 0 2 1 FIGURE 17-7: 3 VDD (V) 4 6 5 PIC12F609/615/617 IDD INTOSC (8 MHz) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-8: PIC12F609/615617 IDD EXTRC (4 MHz) vs. VDD 800 Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 700 600 IDD EXTRC (µA) Typical 500 400 300 200 100 0 1 FIGURE 17-9: 2 4 3 5 VDD (V) 6 PIC12F609/615/617 IDD HS (20 MHz) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-10: PIC12F609/615/617 IPD BASE vs. VDD 9 Extended Typical: Statistical Mean @25°C 8 Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 7 IPD BASE (µA) 6 5 4 3 2 Industrial 1 Typical 0 2 1 FIGURE 17-11: 3 4 VDD (V) 6 5 PIC12F609/615/617 IPD COMPARATOR (SINGLE ON) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-12: PIC12F609/615/617 IPD WDT vs. VDD IPD WDT (µA) 20 Extended 18 Typical: Statistical Mean @25°C 16 Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 14 12 Industrial 10 Typical 8 6 4 2 0 2 1 4 3 6 5 VDD (V) FIGURE 17-13: PIC12F609/615/617 IPD BOR vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-14: PIC12F609/615/617 IPD CVREF (LOW RANGE) vs. VDD 140 Typical: Statistical Mean @25°C Maximum Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) 120 Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typical 100 IPD CVREF (µA) 80 60 40 20 0 2 1 4 3 6 5 VDD (V) FIGURE 17-15: PIC12F609/615/617 IPD CVREF (HI RANGE) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-16: PIC12F609/615/617 IPD T1OSC vs. VDD 25 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) IPD T1OSC (µA) 20 Extended 15 Industrial 10 Typical 5 0 2 1 4 3 6 5 VDD (V) FIGURE 17-17: PIC12F615/617 IPD A/D vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-18: PIC12HV609/615 IDD LP (32 kHz) vs. VDD 450 Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 400 350 IDD LP (µA) 300 Typical 250 200 150 100 50 0 2 1 3 5 4 VDD (V) FIGURE 17-19: PIC12HV609/615 IDD EC (1 MHz) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-21: PIC12HV609/615 IDD XT (1 MHz) vs. VDD 900 800 IDD XT (µA) Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 700 600 Typical 500 400 300 200 100 0 2 1 3 5 4 VDD (V) FIGURE 17-22: PIC12HV609/615 IDD XT (4 MHz) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-24: PIC12HV609/615 IDD INTOSC (8 MHz) vs. VDD IDD INTOSC (µA) 2000 Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1500 Typical 1000 500 0 1 2 3 5 4 VDD (V) FIGURE 17-25: PIC12HV609/615 IDD EXTRC (4 MHz) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-27: PIC12HV609/615 IPD COMPARATOR (SINGLE ON) vs. VDD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 500 Maximum 400 IPD CMP (µA) Typical 300 200 100 0 2 1 3 5 4 VDD (V) FIGURE 17-28: PIC12HV609/615 IPD WDT vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-30: PIC12HV609/615 IPD CVREF (LOW RANGE) vs. VDD 500 400 IPD CVREF (µA) Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typical 300 200 100 0 2 1 3 5 4 VDD (V) FIGURE 17-31: PIC12HV609/615 IPD CVREF (HI RANGE) vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-33: PIC12HV615 IPD A/D vs. VDD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 400 350 Maximum IPD A2D (µA) 300 Typical 250 200 150 100 50 0 2 FIGURE 17-34: 3 4 VDD (V) 5 VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 0.6 Max. 85°C VOL (V) 0.5 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.
PIC12F609/615/617/12HV609/615 FIGURE 17-35: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.40 Max. 125°C 0.35 Max. 85°C VOL (V) 0.30 0.25 Typ. 25°C 0.20 Min. -40°C 0.15 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 17-36: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.
PIC12F609/615/617/12HV609/615 FIGURE 17-37: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 17-38: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ.
PIC12F609/615/617/12HV609/615 FIGURE 17-39: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.5 VIH Min. -40°C VIN (V) 3.0 2.5 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-40: TYPICAL HFINTOSC START-UP TIMES vs.
PIC12F609/615/617/12HV609/615 FIGURE 17-41: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Time (µs) 20 15 85°C 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-42: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 10 9 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 8 7 Time (s) 85°C 6 25°C 5 -40°C 4 3 2 1 0 2.0 2.5 3.
PIC12F609/615/617/12HV609/615 FIGURE 17-43: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-44: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (85°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 FIGURE 17-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41302D-page 190 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 FIGURE 17-47: 0.6V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 0.61 2.5V Reference Voltage (V) 0.6 3V 4V 0.59 5V 0.58 5.5V 0.57 0.56 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 17-48: 1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL) Reference Voltage (V) 1.26 2.5V 1.25 3V 1.24 4V 5V 1.23 5.5V 1.22 1.21 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 17-49: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 5.
PIC12F609/615/617/12HV609/615 FIGURE 17-50: SHUNT REGULATOR VOLTAGE vs. TEMP (TYPICAL) Shunt Regulator Voltage (V) 5.16 5.14 5.12 5.1 50 mA 5.08 40 mA 5.06 5.04 20 mA 5.02 15 mA 5 10 mA 4.98 4 mA 4.96 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 17-51: COMPARATOR RESPONSE TIME (RISING EDGE) 1000 900 Max. 125°C Response Time (nS) 800 700 600 500 Note: VCM = (VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100mV to VCM - 20mV Max. 85°C 400 300 Typ.
PIC12F609/615/617/12HV609/615 FIGURE 17-52: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 Max. 125°C 800 Response Time (nS) 700 600 500 Note: VCM = (VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM - 100mV to VCM + 20MV Max. 85°C 400 300 Typ. 25°C 200 Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) WDT TIME-OUT PERIOD vs. VDD OVER TEMPERATURE FIGURE 17-53: 55 50 45 40 Time (ms) 35 30 125°C 25 85°C 20 25°C 15 -40°C 10 5 1.5 2 2.5 3 3.5 4 4.5 5 5.
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 194 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 18.0 PACKAGING INFORMATION 18.1 Package Marking Information 8-Lead PDIP (.300”) Example XXFXXX/P 017 e3 0610 XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (.150”) Example XXXXXXXX XXXXYYWW NNN PICXXCXX /SN0610 e3 017 8-Lead MSOP Example XXXXXX YWWNNN 602/MS 610017 8-Lead DFN (3x3 mm) Example XXXX YYWW NNN XXXX 0610 017 8-Lead DFN (4x4 mm) (for PIC12F609/615/HV609/615 devices only) XXXXXX XXXXXX YYWW NNN Legend: XXXXXX XXXX e3 0610 017 XX...
PIC12F609/615/617/12HV609/615 18.2 Package Details The following sections give the technical details of the packages.
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PIC12F609/615/617/12HV609/615 APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: Revision A MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX Family of devices. This is a new data sheet. Revision B (05/2008) B.1 Added Graphs. Revised 28-Pin ICD Pinout, Electrical Specifications Section, Package Details.
PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 204 2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615 INDEX A A/D Specifications.................................................... 164, 165 Absolute Maximum Ratings .............................................. 143 AC Characteristics Industrial and Extended ............................................ 156 Load Conditions ........................................................ 155 ADC Acquisition Requirements ........................................... 86 Associated registers....................................................
PIC12F609/615/617/12HV609/615 Initializing GPIO .......................................................... 43 Saving Status and W Registers in RAM ................... 121 Writing to Flash Program Memory .............................. 34 Code Protection ................................................................ 124 Comparator ......................................................................... 67 Associated registers.................................................... 78 Control ..................
PIC12F609/615/617/12HV609/615 RLF ........................................................................... 136 RRF........................................................................... 136 SLEEP ...................................................................... 136 SUBLW ..................................................................... 136 SUBWF ..................................................................... 137 SWAPF ....................................................................
PIC12F609/615/617/12HV609/615 OPTION_REG (Option) .............................................. 55 OSCTUNE (Oscillator Tuning) .................................... 41 PCON (Power Control Register) ................................. 23 PCON (Power Control) ............................................. 113 PIE1 (Peripheral Interrupt Enable 1) ........................... 21 PIR1 (Peripheral Interrupt Register 1) ........................ 22 PWM1CON (Enhanced PWM Control) .....................
PIC12F609/615/617/12HV609/615 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC12F609/615/617/12HV609/615 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC12F609/615/617/12HV609/615 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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