Datasheet
Table Of Contents
- High-Performance RISC CPU:
- Special Microcontroller Features:
- Low-Power Features/CMOS Technology:
- Peripheral Features:
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 General Description
- 2.0 PIC12F519 Device Varieties
- 3.0 Architectural Overview
- 4.0 Memory Organization
- 5.0 Flash Data Memory Control
- 6.0 I/O Port
- 7.0 Timer0 Module and TMR0 Register
- 8.0 Special Features Of The CPU
- 8.1 Configuration Bits
- 8.2 Oscillator Configurations
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
- 8.6 Watchdog Timer (WDT)
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF)
- 8.8 Power-down Mode (Sleep)
- 8.9 Program Verification/Code Protection
- 8.10 ID Locations
- 8.11 In-Circuit Serial Programming™
- 9.0 Instruction Set Summary
- 10.0 Development Support
- 10.1 MPLAB Integrated Development Environment Software
- 10.2 MPASM Assembler
- 10.3 MPLAB C18 and MPLAB C30 C Compilers
- 10.4 MPLINK Object Linker/ MPLIB Object Librarian
- 10.5 MPLAB ASM30 Assembler, Linker and Librarian
- 10.6 MPLAB SIM Software Simulator
- 10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 10.8 MPLAB REAL ICE In-Circuit Emulator System
- 10.9 MPLAB ICD 2 In-Circuit Debugger
- 10.10 MPLAB PM3 Device Programmer
- 10.11 PICSTART Plus Development Programmer
- 10.12 PICkit 2 Development Programmer
- 10.13 Demonstration, Development and Evaluation Boards
- 11.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 11.1 DC Characteristics
- 11.2 Timing Parameter Symbology and Load Conditions – PIC12F519
- 11.3 AC Characteristics
- TABLE 11-5: External Clock Timing Requirements
- TABLE 11-6: Calibrated Internal RC Frequencies
- FIGURE 11-5: I/O Timing
- TABLE 11-7: Timing Requirements
- FIGURE 11-6: Reset, Watchdog Timer and Device Reset Timer Timing
- TABLE 11-8: Reset, Watchdog Timer and Device Reset Timer – PIC12F519
- TABLE 11-9: DRT (Device Reset Timer Period)
- FIGURE 11-7: Timer0 Clock Timings
- TABLE 11-10: Timer0 Clock Requirements
- TABLE 11-11: Flash Data Memory Write/Erase Requirements
- 12.0 DC and AC Characteristics Graphs and Charts
- FIGURE 12-1: Typical Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-2: Maximum Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-3: Idd vs. Vdd over fosc (LP Mode)
- FIGURE 12-4: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-5: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-6: Typical WDT Ipd VS. Vdd
- FIGURE 12-7: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 12-8: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 12-9: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 12-10: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 12-11: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 12-12: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 12-13: TTL Input Threshold Vin VS. Vdd
- FIGURE 12-14: Schmitt Trigger Input Threshold Vin VS. Vdd
- FIGURE 12-15: Device Reset Timer (XT and LP) vs. Vdd
- 13.0 Packaging Information
- Appendix A: Revision History
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales
© 2008 Microchip Technology Inc. DS41319B-page 65
PIC12F519
TABLE 11-3: DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating temperature -40°C ≤ T
A ≤ +85°C (industrial)
-40°C ≤ T
A ≤ +125°C (extended)
Operating voltage V
DD range as described in DC specification.
Param
No.
Sym. Characteristic Min. Typ† Max. Units Conditions
V
IL Input Low Voltage
I/O ports
D030 with TTL buffer Vss — 0.8 V For all 4.5 ≤ V
DD ≤ 5.5V
D030A Vss — 0.15 V
DD V Otherwise
D031 with Schmitt Trigger buffer Vss — 0.15 V
DD V
D032 MCLR
, T0CKI Vss — 0.15 VDD V
D033 OSC1 (EXTRC mode) Vss — 0.15 V
DD V (Note 1)
D033A OSC1 (XT and LP modes) Vss — 0.3 V
V
IH Input High Voltage
I/O ports —
D040 with TTL buffer 2.0 — V
DD V4.5 ≤ VDD ≤ 5.5V
D040A 0.25 V
DD
+ 0.8V
—V
DD V Otherwise
D041 with Schmitt Trigger buffer 0.85 V
DD —VDD V For entire VDD range
D042 MCLR, T0CKI 0.85 V
DD —VDD V
D042A OSC1 (EXTRC mode) 0.85 V
DD —VDD V (Note 1)
D043 OSC1 (XT and LP modes) 1.6 — V
DD V
D070 I
PUR I/O PORT weak pull-up current
(5)
50 250 400 μAVDD = 5V, VPIN = VSS
IIL Input Leakage Current
(2), (3)
D060 I/O ports — — ±1 μA Vss ≤ VPIN ≤ VDD, Pin at high-impedance
D061 GP3/MCLR
(4)
—±0.7±5 μA Vss ≤ VPIN ≤ VDD
D063 OSC1 — — ±5 μA Vss ≤ VPIN ≤ VDD, XT and LP osc configuration
Output Low Voltage
D080 I/O ports — — 0.6 V I
OL = 8.5 mA, VDD = 4.5V, –40°C to +85°C
D080A — — 0.6 V I
OL = 7.0 mA, VDD = 4.5V, –40°C to +125°C
Output High Voltage
D090 I/O ports
(3)
VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, –40°C to +85°C
D090A V
DD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, –40°C to +125°C
Capacitive Loading Specs on Output Pins
D101 All I/O pins — — 50 pF
Flash Data Memory
D120 E
D Byte endurance 100K 1M — E/W –40°C ≤ TA ≤ +85°C
D120A E
D Byte endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C
D121 V
DRW VDD for read/write VMIN —5.5 V
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F519 be driven
with external clock in RC mode.
2: The leakage current on the MCLR
pin is strongly dependent on the applied voltage level. The specified levels represent normal operat-
ing conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: This specification applies to GP3/MCLR
configured as GP3 with internal pull-up disabled.
5: This specification applies to all weak pull-up devices, including the weak pull-up found on GP3/MCLR
. The current value listed will be the
same whether or not the pin is configured as GP3 with pull-up enabled or MCLR
.