Datasheet
Table Of Contents
- High-Performance RISC CPU:
- Special Microcontroller Features:
- Low-Power Features/CMOS Technology:
- Peripheral Features:
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 General Description
- 2.0 PIC12F519 Device Varieties
- 3.0 Architectural Overview
- 4.0 Memory Organization
- 5.0 Flash Data Memory Control
- 6.0 I/O Port
- 7.0 Timer0 Module and TMR0 Register
- 8.0 Special Features Of The CPU
- 8.1 Configuration Bits
- 8.2 Oscillator Configurations
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
- 8.6 Watchdog Timer (WDT)
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF)
- 8.8 Power-down Mode (Sleep)
- 8.9 Program Verification/Code Protection
- 8.10 ID Locations
- 8.11 In-Circuit Serial Programming™
- 9.0 Instruction Set Summary
- 10.0 Development Support
- 10.1 MPLAB Integrated Development Environment Software
- 10.2 MPASM Assembler
- 10.3 MPLAB C18 and MPLAB C30 C Compilers
- 10.4 MPLINK Object Linker/ MPLIB Object Librarian
- 10.5 MPLAB ASM30 Assembler, Linker and Librarian
- 10.6 MPLAB SIM Software Simulator
- 10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 10.8 MPLAB REAL ICE In-Circuit Emulator System
- 10.9 MPLAB ICD 2 In-Circuit Debugger
- 10.10 MPLAB PM3 Device Programmer
- 10.11 PICSTART Plus Development Programmer
- 10.12 PICkit 2 Development Programmer
- 10.13 Demonstration, Development and Evaluation Boards
- 11.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 11.1 DC Characteristics
- 11.2 Timing Parameter Symbology and Load Conditions – PIC12F519
- 11.3 AC Characteristics
- TABLE 11-5: External Clock Timing Requirements
- TABLE 11-6: Calibrated Internal RC Frequencies
- FIGURE 11-5: I/O Timing
- TABLE 11-7: Timing Requirements
- FIGURE 11-6: Reset, Watchdog Timer and Device Reset Timer Timing
- TABLE 11-8: Reset, Watchdog Timer and Device Reset Timer – PIC12F519
- TABLE 11-9: DRT (Device Reset Timer Period)
- FIGURE 11-7: Timer0 Clock Timings
- TABLE 11-10: Timer0 Clock Requirements
- TABLE 11-11: Flash Data Memory Write/Erase Requirements
- 12.0 DC and AC Characteristics Graphs and Charts
- FIGURE 12-1: Typical Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-2: Maximum Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-3: Idd vs. Vdd over fosc (LP Mode)
- FIGURE 12-4: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-5: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-6: Typical WDT Ipd VS. Vdd
- FIGURE 12-7: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 12-8: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 12-9: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 12-10: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 12-11: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 12-12: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 12-13: TTL Input Threshold Vin VS. Vdd
- FIGURE 12-14: Schmitt Trigger Input Threshold Vin VS. Vdd
- FIGURE 12-15: Device Reset Timer (XT and LP) vs. Vdd
- 13.0 Packaging Information
- Appendix A: Revision History
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales
© 2008 Microchip Technology Inc. DS41319B-page 49
PIC12F519
9.0 INSTRUCTION SET SUMMARY
The PIC12F519 instruction set is highly orthogonal and
is comprised of three basic categories.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC12F519 instruction is a 12-bit word divided
into an opcode, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The formats for each of the
categories is presented in Figure 9-1, while the various
opcode fields are summarized in Table 9-1.
For byte-oriented instructions, ‘f’ represents a file reg-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
TABLE 9-1: OPCODE FIELD
DESCRIPTIONS
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 μs.
Figure 9-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
0xhhh
where ‘h’ signifies a hexadecimal digit.
FIGURE 9-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
f Register file address (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility with
all Microchip software tools.
d Destination select;
d = 0 (store result in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label Label name
TOS Top-of-Stack
PC Program Counter
WDT Watchdog Timer counter
TO
Time-out bit
PD Power-down bit
dest Destination, either the W register or the specified
register file location
[ ] Options
( ) Contents
→ Assigned to
< > Register bit field
∈ In the set of
italics User defined term (font is courier)
Byte-oriented file register operations
11 6 5 4 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11 8 7 5 4 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Literal and control operations – GOTO instruction
11 9 8 0
OPCODE k (literal)
k = 9-bit immediate value