Datasheet

PIC12F519
DS41319B-page 42 © 2008 Microchip Technology Inc.
TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS
8.3.1 M
CLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR
function. When
programmed, the MCLR
function is tied to the internal
V
DD and the pin is assigned to be a I/O. See Figure 8-6.
FIGURE 8-6: MCLR SELECT
8.4 Power-on Reset (POR)
The PIC12F519 device incorporates an on-chip
Power-on Reset (POR) circuitry, which provides an
internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
V
DD has reached a high enough level for proper
operation. To take advantage of the internal POR,
program the GP3/MCLR
/VPP pin as MCLR and tie
through a resistor to V
DD, or program the pin as GP3, in
which case, an internal weak pull-up resistor is
implemented using a transistor (refer to Table 11-4 for
the pull-up resistor ranges). This will eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for V
DD is specified. See
Section 11.0 “Electrical Characteristics” for details.
When the devices start normal operation (exit the Reset
condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-7.
The Power-on Reset circuit and the Device Reset Timer
(see Section 8.5 “Device Reset Timer (DRT)”) circuit
are closely related. On power-up, the Reset latch is set
and the DRT is reset. The DRT timer begins counting
once it detects MCLR
to be high. After the time-out
period, which is typically 18 ms or 1 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR
is held low is shown
in Figure 8-8. V
DD is allowed to rise and stabilize before
bringing MCLR
high. The chip will actually come out of
Reset T
DRT after MCLR goes high.
In Figure 8-9, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be GP3). The V
DD is stable before
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 8-10 depicts a
problem situation where V
DD rises too slowly. The time
between when the DRT senses that MCLR
is high and
when MCLR
and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
out, V
DD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-9).
For additional information, refer to Application Note
AN522, “Power-Up Considerations” (DS00522)
STATUS Addr: 03h
Power-on Reset 0-01 1xxx
MCLR
Reset during normal operation 0-0u uuuu
MCLR
Reset during Sleep 0-01 0uuu
WDT Reset during Sleep 0-00 0uuu
WDT Reset normal operation 0-00 uuuu
Wake-up from Sleep on pin change 1-01 0uuu
Legend: u = unchanged, x = unknown
GP3/MCLR/VPP
MCLRE
Internal MCLR
GPPU
Note: When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.