Datasheet
Table Of Contents
- High-Performance RISC CPU:
- Special Microcontroller Features:
- Low-Power Features/CMOS Technology:
- Peripheral Features:
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 General Description
- 2.0 PIC12F519 Device Varieties
- 3.0 Architectural Overview
- 4.0 Memory Organization
- 5.0 Flash Data Memory Control
- 6.0 I/O Port
- 7.0 Timer0 Module and TMR0 Register
- 8.0 Special Features Of The CPU
- 8.1 Configuration Bits
- 8.2 Oscillator Configurations
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
- 8.6 Watchdog Timer (WDT)
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF)
- 8.8 Power-down Mode (Sleep)
- 8.9 Program Verification/Code Protection
- 8.10 ID Locations
- 8.11 In-Circuit Serial Programming™
- 9.0 Instruction Set Summary
- 10.0 Development Support
- 10.1 MPLAB Integrated Development Environment Software
- 10.2 MPASM Assembler
- 10.3 MPLAB C18 and MPLAB C30 C Compilers
- 10.4 MPLINK Object Linker/ MPLIB Object Librarian
- 10.5 MPLAB ASM30 Assembler, Linker and Librarian
- 10.6 MPLAB SIM Software Simulator
- 10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 10.8 MPLAB REAL ICE In-Circuit Emulator System
- 10.9 MPLAB ICD 2 In-Circuit Debugger
- 10.10 MPLAB PM3 Device Programmer
- 10.11 PICSTART Plus Development Programmer
- 10.12 PICkit 2 Development Programmer
- 10.13 Demonstration, Development and Evaluation Boards
- 11.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 11.1 DC Characteristics
- 11.2 Timing Parameter Symbology and Load Conditions – PIC12F519
- 11.3 AC Characteristics
- TABLE 11-5: External Clock Timing Requirements
- TABLE 11-6: Calibrated Internal RC Frequencies
- FIGURE 11-5: I/O Timing
- TABLE 11-7: Timing Requirements
- FIGURE 11-6: Reset, Watchdog Timer and Device Reset Timer Timing
- TABLE 11-8: Reset, Watchdog Timer and Device Reset Timer – PIC12F519
- TABLE 11-9: DRT (Device Reset Timer Period)
- FIGURE 11-7: Timer0 Clock Timings
- TABLE 11-10: Timer0 Clock Requirements
- TABLE 11-11: Flash Data Memory Write/Erase Requirements
- 12.0 DC and AC Characteristics Graphs and Charts
- FIGURE 12-1: Typical Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-2: Maximum Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-3: Idd vs. Vdd over fosc (LP Mode)
- FIGURE 12-4: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-5: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-6: Typical WDT Ipd VS. Vdd
- FIGURE 12-7: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 12-8: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 12-9: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 12-10: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 12-11: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 12-12: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 12-13: TTL Input Threshold Vin VS. Vdd
- FIGURE 12-14: Schmitt Trigger Input Threshold Vin VS. Vdd
- FIGURE 12-15: Device Reset Timer (XT and LP) vs. Vdd
- 13.0 Packaging Information
- Appendix A: Revision History
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales
© 2008 Microchip Technology Inc. DS41319B-page 39
PIC12F519
8.2 Oscillator Configurations
8.2.1 OSCILLATOR TYPES
The PIC12F519 device can be operated in up to four
different oscillator modes. The user can program using
the Configuration bits (FOSC<1:0>), to select one of
these modes:
• LP: Low-Power Crystal
• XT: Crystal/Resonator
• INTRC: Internal 4 MHz or 8 MHz Oscillator
• EXTRC: External Resistor/Capacitor
8.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT or LP modes, a crystal or ceramic resonator is
connected to the (GP5)/OSC1/(CLKIN) and
(GP4)/OSC2 pins to establish oscillation (Figure 8-1).
The PIC12F519 oscillator designs require the use of a
parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers
specifications. When in XT or LP modes, the device can
have an external clock source drive the
(GP5)/OSC1/CLKIN pin (Figure 8-2). When the part is
used in this fashion, the output drive levels on the OSC2
pin are very weak. This pin should be left open and
unloaded. Also when using this mode, the external clock
should observe the frequency limits for the clock mode
chosen (XT or LP).
FIGURE 8-1: CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
(XT OR LP OSC
CONFIGURATION)
FIGURE 8-2: EXTERNAL CLOCK INPUT
OPERATION (XT OR LP
OSC CONFIGURATION)
TABLE 8-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
TABLE 8-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR –
PIC12F519
(2)
Note 1: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may
be required.
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF approx. value = 10 MΩ.
C1
(1)
C2
(1)
XTAL
OSC2
OSC1
RF
(3)
Sleep
To internal
logic
RS
(2)
PIC12F519
Osc
Type
Resonator
Freq.
Cap. Range
C1
Cap. Range
C2
XT 4.0 MHz 30 pF 30 pF
Note: Component values shown are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for
appropriate values of external compo-
nents.
Osc
Type
Resonator
Freq.
Cap.Range
C1
Cap. Range
C2
LP 32 kHz
(1)
15 pF 15 pF
XT 200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
2: Component values shown are for design
guidance only. Rs may be required to
avoid overdriving crystals with low drive
level specification. Since each crystal has
its own characteristics, the user should
consult the crystal manufacturer for
appropriate values of external compo-
nents.
Clock from
ext. system
OSC1
OSC2
Open
PIC12F519