Datasheet

PIC12F519
DS41319B-page 30 © 2008 Microchip Technology Inc.
6.4 I/O Programming Considerations
6.4.1 BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit 5 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit 5 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bidirectional
I/O pin (say bit 0) and it is defined as an input at this
time, the input signal present on the pin itself would be
read into the CPU and rewritten to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown.
Example 6-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The resulting high output currents may damage
the chip.
EXAMPLE 6-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
6.4.2 SUCCESSIVE OPERATIONS ON
I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 6-6).
Therefore, care must be exercised if a write followed by
a read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
FIGURE 6-6: SUCCESSIVE I/O OPERATION
;Initial GPIO Settings
;GPIO<5:3> Inputs
;GPIO<2:0> Outputs
;
; GPIO latch GPIO pins
; ---------- ----------
BCF GPIO, 5 ;--01 -ppp --11 pppp
BCF GPIO, 4 ;--10 -ppp --11 pppp
MOVLW 007h;
TRIS GPIO ;--10 -ppp --11 pppp
;
Note 1: The user may have expected the pin values to
be ‘--00 pppp’. The 2nd BCF caused GP5 to
be latched as the pin value (High).
PC PC + 1 PC + 2
PC + 3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
GP<5:0>
MOVWF GPIO NOP
Port pin
sampled here
NOPMOVF GPIO, W
Instruction
Executed
MOVWF GPIO
(Write to GPIO)
NOPMOVF PORTB,W
This example shows a write to GPIO followed
by a read from GPIO.
Data setup time = (0.25 T
CY – TPD)
where: T
CY = instruction cycle.
T
PD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
(Read PORTB)
Port pin
written here