Datasheet
Table Of Contents
- High-Performance RISC CPU:
- Special Microcontroller Features:
- Low-Power Features/CMOS Technology:
- Peripheral Features:
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 General Description
- 2.0 PIC12F519 Device Varieties
- 3.0 Architectural Overview
- 4.0 Memory Organization
- 5.0 Flash Data Memory Control
- 6.0 I/O Port
- 7.0 Timer0 Module and TMR0 Register
- 8.0 Special Features Of The CPU
- 8.1 Configuration Bits
- 8.2 Oscillator Configurations
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
- 8.6 Watchdog Timer (WDT)
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF)
- 8.8 Power-down Mode (Sleep)
- 8.9 Program Verification/Code Protection
- 8.10 ID Locations
- 8.11 In-Circuit Serial Programming™
- 9.0 Instruction Set Summary
- 10.0 Development Support
- 10.1 MPLAB Integrated Development Environment Software
- 10.2 MPASM Assembler
- 10.3 MPLAB C18 and MPLAB C30 C Compilers
- 10.4 MPLINK Object Linker/ MPLIB Object Librarian
- 10.5 MPLAB ASM30 Assembler, Linker and Librarian
- 10.6 MPLAB SIM Software Simulator
- 10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 10.8 MPLAB REAL ICE In-Circuit Emulator System
- 10.9 MPLAB ICD 2 In-Circuit Debugger
- 10.10 MPLAB PM3 Device Programmer
- 10.11 PICSTART Plus Development Programmer
- 10.12 PICkit 2 Development Programmer
- 10.13 Demonstration, Development and Evaluation Boards
- 11.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 11.1 DC Characteristics
- 11.2 Timing Parameter Symbology and Load Conditions – PIC12F519
- 11.3 AC Characteristics
- TABLE 11-5: External Clock Timing Requirements
- TABLE 11-6: Calibrated Internal RC Frequencies
- FIGURE 11-5: I/O Timing
- TABLE 11-7: Timing Requirements
- FIGURE 11-6: Reset, Watchdog Timer and Device Reset Timer Timing
- TABLE 11-8: Reset, Watchdog Timer and Device Reset Timer – PIC12F519
- TABLE 11-9: DRT (Device Reset Timer Period)
- FIGURE 11-7: Timer0 Clock Timings
- TABLE 11-10: Timer0 Clock Requirements
- TABLE 11-11: Flash Data Memory Write/Erase Requirements
- 12.0 DC and AC Characteristics Graphs and Charts
- FIGURE 12-1: Typical Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-2: Maximum Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-3: Idd vs. Vdd over fosc (LP Mode)
- FIGURE 12-4: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-5: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-6: Typical WDT Ipd VS. Vdd
- FIGURE 12-7: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 12-8: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 12-9: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 12-10: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 12-11: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 12-12: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 12-13: TTL Input Threshold Vin VS. Vdd
- FIGURE 12-14: Schmitt Trigger Input Threshold Vin VS. Vdd
- FIGURE 12-15: Device Reset Timer (XT and LP) vs. Vdd
- 13.0 Packaging Information
- Appendix A: Revision History
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales
© 2008 Microchip Technology Inc. DS41319B-page 17
PIC12F519
4.4 OPTION Register
The OPTION register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION regis-
ter. A Reset sets the OPTION<7:0> bits.
Note: If the T0SC bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-2: OPTION: OPTION REGISTER
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
GPW
U GPPU T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit x = Bit is unknown
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 GPW
U: Enable Wake-up On Pin Change bit
1 = Disabled
0 = Enabled
bit 6 GPP
U: Enable Weak Pull-ups bit
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate