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Table Of Contents

High-Performance RISC CPU:
Special Microcontroller Features:
Low-Power Features/CMOS Technology:
Peripheral Features:
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 General Description
- 1.1 Applications
  - TABLE 1-1: Features and memory of PIC12F519
2.0 PIC12F519 Device Varieties
- 2.1 Quick Turn Programming (QTP) Devices
- 2.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices
3.0 Architectural Overview
- TABLE 3-1: PIC12F519 Memory
- FIGURE 3-1: PIC12F519 ARCHITECTURAL Block Diagram
- TABLE 3-2: PIC12F519 Pinout Description
- 3.1 Clocking Scheme/Instruction Cycle
- 3.2 Instruction Flow/Pipelining
  - FIGURE 3-2: Clock/Instruction Cycle
  - EXAMPLE 3-1: Instruction Pipeline Flow
4.0 Memory Organization
- 4.1 Program Memory Organization for the PIC12F519
  - FIGURE 4-1: Memory Map
- 4.2 Data Memory (SRAM and FSRs)
  - 4.2.1 General Purpose Register File
    - FIGURE 4-2: Register File Map
  - 4.2.2 Special Function Registers
    - TABLE 4-1: Special Function Register Summary
- 4.3 STATUS register
  - Register 4-1: STATUS: STATUS Register
- 4.4 OPTION Register
  - Register 4-2: OPTION: OPTION Register
- 4.5 OSCCAL Register
  - Register 4-3: OSCCAL: Oscillator Calibration Register
- 4.6 Program Counter
  - FIGURE 4-3: Loading of PC Branch Instructions
  - 4.6.1 Effects Of Reset
- 4.7 Stack
- 4.8 Indirect Data Addressing: INDF and FSR Registers
  - EXAMPLE 4-1: How to Clear RAM Using Indirect Addressing
  - FIGURE 4-4: Direct/Indirect Addressing
5.0 Flash Data Memory Control
- 5.1 Reading Flash Data Memory
- 5.2 Writing and Erasing Flash Data Memory
  - 5.2.1 Erasing Flash Data Memory
  - 5.2.2 Writing to Flash Data Memory
- 5.3 Write Verify
- 5.4 Code Protection
6.0 I/O Port
- 6.1 GPIO
- 6.2 TRIS Registers
- 6.3 I/O Interfacing
- 6.4 I/O Programming Considerations
  - 6.4.1 Bidirectional I/O Ports
    - EXAMPLE 6-1: Read-modify-write Instructions on an I/O Port
  - 6.4.2 Successive Operations on I/O Ports
    - FIGURE 6-6: Successive I/O OperatioN
7.0 Timer0 Module and TMR0 Register
- FIGURE 7-1: Timer0 Block Diagram
- FIGURE 7-2: TIMER0 Timing: Internal Clock/No Prescale
- FIGURE 7-3: TIMER0 Timing: Internal Clock/Prescale 1:2
- TABLE 7-1: Registers Associated With TIMER0
- 7.1 Using Timer0 with an External Clock
  - 7.1.1 External Clock Synchronization
  - 7.1.2 TIMER0 Increment Delay
    - FIGURE 7-4: TIMER0 Timing with External Clock
- 7.2 Prescaler
  - 7.2.1 Switching Prescaler Assignment
8.0 Special Features Of The CPU
- 8.1 Configuration Bits
  - Register 8-1: CONFIG: Configuration Word Register(1)
- 8.2 Oscillator Configurations
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
  - TABLE 8-5: DRT (Device Reset Timer Period)
- 8.6 Watchdog Timer (WDT)
  - 8.6.1 WDT Period
  - 8.6.2 WDT Programming Considerations
    - FIGURE 8-11: Watchdog Timer Block Diagram
    - TABLE 8-6: Summary of Register Associated with the Watchdog Timer
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF)
  - TABLE 8-7: TO/PD/(GPWUF) Status After Reset
- 8.8 Power-down Mode (Sleep)
  - 8.8.1 Sleep
  - 8.8.2 Wake-up from Sleep
- 8.9 Program Verification/Code Protection
- 8.10 ID Locations
- 8.11 In-Circuit Serial Programming™
  - FIGURE 8-12: Typical In-Circuit Serial Programming Connection
9.0 Instruction Set Summary
- TABLE 9-1: Opcode Field Descriptions
- FIGURE 9-1: General Format for Instructions
- TABLE 9-2: Instruction Set Summary
10.0 Development Support
- 10.1 MPLAB Integrated Development Environment Software
- 10.2 MPASM Assembler
- 10.3 MPLAB C18 and MPLAB C30 C Compilers
- 10.4 MPLINK Object Linker/ MPLIB Object Librarian
- 10.5 MPLAB ASM30 Assembler, Linker and Librarian
- 10.6 MPLAB SIM Software Simulator
- 10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 10.8 MPLAB REAL ICE In-Circuit Emulator System
- 10.9 MPLAB ICD 2 In-Circuit Debugger
- 10.10 MPLAB PM3 Device Programmer
- 10.11 PICSTART Plus Development Programmer
- 10.12 PICkit 2 Development Programmer
- 10.13 Demonstration, Development and Evaluation Boards
11.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
  - FIGURE 11-1: PIC12F519 Voltage-Frequency Graph, -40°C £ ta £ +125°C
  - FIGURE 11-2: Maximum Oscillator Frequency Table
- 11.1 DC Characteristics
- 11.2 Timing Parameter Symbology and Load Conditions – PIC12F519
  - FIGURE 11-3: Load Conditions – PIC12F519
  - FIGURE 11-4: External Clock Timing – PIC12F519
- 11.3 AC Characteristics
12.0 DC and AC Characteristics Graphs and Charts
- FIGURE 12-1: Typical Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-2: Maximum Idd vs. Fosc Over Vdd (XT, EXTRC mode)
- FIGURE 12-3: Idd vs. Vdd over fosc (LP Mode)
- FIGURE 12-4: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-5: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 12-6: Typical WDT Ipd VS. Vdd
- FIGURE 12-7: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 12-8: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 12-9: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 12-10: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 12-11: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 12-12: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 12-13: TTL Input Threshold Vin VS. Vdd
- FIGURE 12-14: Schmitt Trigger Input Threshold Vin VS. Vdd
- FIGURE 12-15: Device Reset Timer (XT and LP) vs. Vdd
13.0 Packaging Information
- 13.1 Package Marking Information
Appendix A: Revision History
INDEX
The Microchip Web Site
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PIC12F519

4.2 Data Memory (SRAM and FSRs)

Data memory is composed of registers or bytes of

SRAM. Therefore, data memory for a device is speci-

fied by its register file. The register file is divided into

two functional groups: Special Function Registers

(SFR) and General Purpose Registers (GPR).

The Special Function Registers include the TMR0

EEADR registers provide for interface with the Flash

data memory.

The PIC12F519 register file is composed of 10 Special

Function Registers and 41 General Purpose Registers.

4.2.1 GENERAL PURPOSE REGISTER

FILE

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.8 “Indirect Data Addressing:

INDF and FSR Registers”.

FIGURE 4-2: REGISTER FILE MAP

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 4-1).

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF

(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

0Fh

10h

Bank 0 Bank 1

3Fh

30h

20h

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

08h

Note 1: Not a physical register.

FSR<5> 01

2Fh

09h

0Ah

INDF

(1)

EECON

PCL

STATUS

FSR

EEDATA

EEADR

Address map

back to

addresses

in Bank 0