Datasheet

Table Of Contents
© 2008 Microchip Technology Inc. DS41319B-page 13
PIC12F519
4.0 MEMORY ORGANIZATION
The PIC12F519 memory is organized into program
memory and data memory (SRAM). The self-writable
portion of the program memory called Flash data mem-
ory, is located at addresses 400h-43Fh. As the device
has more than 512 bytes of program memory, a paging
scheme is used. Program memory pages are accessed
using STATUS register bit, PA0. For the PIC12F519,
with data memory register files of more than 32 regis-
ters, a banking scheme is used. Data memory banks
are accessed using the File Select Register (FSR).
4.1 Program Memory Organization for
the PIC12F519
The PIC12F519 device has an 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space.
Only the first 1K x 12 (0000h-03FFh) are physically
implemented (see Figure 4-1). Accessing a location
above these boundaries will cause a wrap-around
within the 1K x 12 space. The effective Reset vector
is a 0000h (see Figure 4-1). Location 03FFh contains
the internal clock oscillator calibration value. This
value should never be overwritten.
FIGURE 4-1: MEMORY MAP
CALL, RETLW
PC<11:0>
Stack Level 1
Stack Level 2
User Memory
Space
10
0000h
7FFh
01FFh
0200h
On-chip Program
Memory
Reset Vector
(1)
Note 1: Address 0000h becomes the effective
Reset vector. Location 03FFh contains
the MOVLW XX internal oscillator
calibration value.
2: Flash data memory is non-executable.
512 Word
1024 Word
03FFh
0400h
On-chip Program
Memory
Flash Data Memory
043Fh
0440h
Flash Data Memory
Space