PIC12F519 Data Sheet 8-Pin, 8-Bit Flash Microcontrollers *8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC12F519 8-Pin, 8-Bit Flash Microcontroller High-Performance RISC CPU: Low-Power Features/CMOS Technology: • Only 33 Single-Word Instructions • All Single-Cycle Instructions except for Program Branches which are Two-Cycle • Two-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes for Data and Instructions • Operating Speed: - DC – 8 MHz Oscillator - DC – 500 ns instruction cycle • On-chip Flash Program Memory - 1024 x 12 • General Purpose Registers (SRAM) - 41 x 8 • Flash Data Memor
PIC12F519 FIGURE 1: PIC12F519 8-PIN PDIP, SOIC, MSOP, 2X3 DFN DIAGRAM VDD 1 GP5/OSC1/CLKIN 2 GP4/OSC2 3 GP3/MCLR/VPP 4 PIC12F519 PDIP, SOIC, MSOP 8 7 VSS 6 GP1/ICSPCLK 5 GP2/T0CKI GP0/ICSPDAT VDD 1 GP5/OSC1/CLKIN 2 GP4/OSC2 3 GP3/MCLR/VPP 4 Program Memory PIC12F519 DFN 8 VSS 7 GP0/ICSPDAT 6 GP1/ICSPCLK 5 GP2/T0CKI Data Memory Device PIC12F519 DS41319B-page 2 Flash (words) SRAM (bytes) Flash (bytes) 1024 41 64 I/O Timers 8-bit 6 1 © 2008 Microchip Technology I
PIC12F519 Table of Contents 1.0 General Description .................................................................................................................................................................. 5 2.0 PIC12F519 Device Varieties .................................................................................................................................................... 7 3.0 Architectural Overview ......................................................................................
PIC12F519 NOTES: DS41319B-page 4 © 2008 Microchip Technology Inc.
PIC12F519 1.0 GENERAL DESCRIPTION The PIC12F519 device from Microchip Technology is low-cost, high-performance, 8-bit, fully-static, Flashbased CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/single-cycle instructions. All instructions are single cycle except for program branches, which take two cycles. The PIC12F519 device delivers performance an order of magnitude higher than their competitors in the same price category.
PIC12F519 NOTES: DS41319B-page 6 © 2008 Microchip Technology Inc.
PIC12F519 2.0 PIC12F519 DEVICE VARIETIES When placing orders, please use the PIC12F519 Product Identification System at the back of this data sheet to specify the correct part number. A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. 2.1 Quick Turn Programming (QTP) Devices 2.
PIC12F519 NOTES: DS41319B-page 8 © 2008 Microchip Technology Inc.
PIC12F519 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12F519 device can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12F519 device uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus.
PIC12F519 FIGURE 3-1: PIC12F519 ARCHITECTURAL BLOCK DIAGRAM Flash Program Memory 1K x 12 11 Flash Data Memory 64x8 8 Data Bus Program Counter GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP55/OSC1/CLKIN RAM 41 x 8 File Registers Stack 1 Stack 2 Program 12 Bus RAM Addr GPI/O 9 Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg STATUS Reg 8 3 MUX Device Reset Timer Instruction Decode & Control OSC1/CLKIN OSC2 Timing Generation Internal RC OSC Power-on Reset Wat
PIC12F519 TABLE 3-2: Name PIC12F519 PINOUT DESCRIPTION Function GP0/ICSPDAT GP1/ICSPCLK GP4/OSC2 GP5/OSC1/ CLKIN VDD VSS Legend: Description TTL CMOS Bidirectional I/O port with weak pull-up ICSPDAT I/O ST CMOS ICSP™ mode Schmitt Trigger GP1 I/O TTL CMOS I ST — GP2 GP3/MCLR/VPP Input Type Output Type I/O ICSPCLK GP2/T0CKI Type GP0 Bidirectional I/O port with weak pull-up ICSP™ mode Schmitt Trigger I/O TTL CMOS T0CKI I ST — Timer0 clock input Bidirectional I/O port GP3 I
PIC12F519 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g.
PIC12F519 The PIC12F519 memory is organized into program memory and data memory (SRAM). The self-writable portion of the program memory called Flash data memory, is located at addresses 400h-43Fh. As the device has more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using STATUS register bit, PA0. For the PIC12F519, with data memory register files of more than 32 registers, a banking scheme is used.
PIC12F519 4.2 Data Memory (SRAM and FSRs) Data memory is composed of registers or bytes of SRAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). The Special Function Registers include the TMR0 register, the Program Counter Low (PCL), the STATUS register, the I/O register (port) and the File Select Register (FSR).
PIC12F519 TABLE 4-1: Addr Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset — — TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 --11 1111 N/A TRISGPIO N/A OPTION Contains Control Bits to Configure Timer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx 02h(1) PCL Low Order 8 bits of PC
PIC12F519 4.3 For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). STATUS register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits from the STATUS register.
PIC12F519 4.4 By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits. OPTION Register The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. REGISTER 4-2: Note: If the T0SC bit is set to ‘1’, it will override the TRIS function on the T0CKI pin.
PIC12F519 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the 8 MHz internal oscillator macro. It contains 7 bits of calibration that uses a two’s complement scheme for controlling the oscillator speed. See Register 4-3 for details.
PIC12F519 4.6 4.6.1 Program Counter EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction).
PIC12F519 4.8 EXAMPLE 4-1: Indirect Data Addressing: INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. NEXT Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although Status bits may be affected).
PIC12F519 5.0 FLASH DATA MEMORY CONTROL The Flash data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFRs). 5.
PIC12F519 5.2.2 WRITING TO FLASH DATA MEMORY EXAMPLE 4: WRITE VERIFY OF DATA EEPROM Once a cell is erased, new data can be written. Program execution is suspended during the write cycle. The following sequence must be performed for a single byte write. MOVF EEDATA, W ;EEDATA has not changed BSF EECON, RD ;Read the value written XORWF EEDATA, W ; 1. 2. 3. BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error Load EEADR with the address. Load EEDATA with the data to write.
PIC12F519 6.0 I/O PORT 6.2 The Output Driver Control registers are loaded with the contents of the W Register by executing the TRIS f instruction. A ‘1’ from a TRISGPIO Register bit puts the corresponding output driver in a high-impedance (Input) mode. A ‘0’ puts the contents of the output data latch on the selected pins, enabling the output buffer. As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g.
PIC12F519 REGISTER 6-1: GPIO: GPIO REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GP<5:0>: GPIO I/O Pin bits 1 = GPIO pin is >VIH min. 0 = GPIO pin is
PIC12F519 6.3 I/O Interfacing The equivalent circuit for an I/O port pin is shown in Figure 6-1. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO, W). The outputs are latched and remain unchanged until the output latch is rewritten.
PIC12F519 FIGURE 6-2: GP2/TOCK1 • General Purpose I/O • A Clock Input for Timer0 Q D Data VDD I/O Pin Data Latch WR CK WREG Q Q D TRIS Latch CK TRIS ‘F’ VSS Q TOCS RD Port To Timer0 DS41319B-page 26 © 2008 Microchip Technology Inc.
PIC12F519 FIGURE 6-3: GP4/OSC2 • General Purpose I/O • A crystal resonator connection VDD From OSC1 DATA BUS Oscillator Circuit Q D I/O Pin Data Latch WR PORT WREG CK Q Q D TRIS Latch TRIS ‘F’ CK VSS Q INTOSC RC RD PORT © 2008 Microchip Technology Inc.
PIC12F519 FIGURE 6-4: GP5/OSC1/CLKIN VDD Oscillator Circuit From OSC2 DATA BUS Q D I/O Pin Data Latch WR PORT WREG CK Q Q D TRIS Latch TRIS ‘F’ CK VSS Q • General Purpose I/O • A crystal resonator connection • A clock input RD PORT DS41319B-page 28 © 2008 Microchip Technology Inc.
PIC12F519 FIGURE 6-5: GP3 (WITH WEAK PULLUP AND WAKE-UP ON CHANGE) GPPU Weak MCLRE Reset Input Pin(1) VSS Data Bus RD Port Q D Wake-up on change latch CK Pin Change Note 1: GP3/MCLR pin has a protection diode to VSS only.
PIC12F519 6.4 EXAMPLE 6-1: I/O Programming Considerations 6.4.1 BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs.
PIC12F519 7.0 Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.1 “Using Timer0 with an External Clock”.
PIC12F519 FIGURE 7-3: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC – 1 Instruction Fetch PC PC + 1 MOVWF TMR0 T0 Timer0 T0 + 1 Instruction Executed Name PC + 4 PC + 5 PC + 6 Read TMR0 reads NT0 Read TMR0 reads NT0 NT0 + 1 Read TMR0 reads NT0 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 Value on
PIC12F519 7.1 Using Timer0 with an External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
PIC12F519 7.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section 8.6 “Watchdog Timer (WDT)”). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice versa.
PIC12F519 BLOCK DIAGRAM OF THE TIMER0/ WDT PRESCALER(1) FIGURE 7-5: TCY (= FOSC/4) Data Bus 0 T0CKI pin 1 8 M U X 1 M U X 0 Sync 2 Cycles TMR0 Reg T0SE T0CS 0 Watchdog Timer 1 M U X PSA 8-bit Prescaler 8 8-to-1 MUX PS<2:0> PSA WDT Enable bit 1 0 MUX PSA WDT Time-Out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. © 2008 Microchip Technology Inc.
PIC12F519 NOTES: DS41319B-page 36 © 2008 Microchip Technology Inc.
PIC12F519 8.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC12F519 microcontroller has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection.
PIC12F519 REGISTER 8-1: — CONFIG: CONFIGURATION WORD REGISTER(1) CPDF IOSCFS MCLRE CP WDTE bit 7 FOSC1 FOSC0 bit 0 bit 7 Unimplemented: Read as ‘1’ bit 6 CPDF: Code Protection bit - Flash Data Memory 1 = Code protection off 0 = Code protection on bit 5 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC frequency 0 = 4 MHz INTOSC frequency bit 4 MCLRE: Master Clear Enable bit 1 = GP3/MCLR pin functions as MCLR 0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD bit
PIC12F519 8.2 FIGURE 8-2: Oscillator Configurations 8.2.1 OSCILLATOR TYPES The PIC12F519 device can be operated in up to four different oscillator modes. The user can program using the Configuration bits (FOSC<1:0>), to select one of these modes: • • • • EXTERNAL CLOCK INPUT OPERATION (XT OR LP OSC CONFIGURATION) LP: XT: INTRC: EXTRC: 8.2.
PIC12F519 8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.
PIC12F519 PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. Note: Erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator.
PIC12F519 TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h Power-on Reset 0-01 1xxx MCLR Reset during normal operation 0-0u uuuu MCLR Reset during Sleep 0-01 0uuu WDT Reset during Sleep 0-00 0uuu WDT Reset normal operation 0-00 uuuu Wake-up from Sleep on pin change 1-01 0uuu Legend: u = unchanged, x = unknown 8.3.1 MCLR ENABLE This Configuration bit, when unprogrammed (left in the ‘1’ state), enables the external MCLR function.
PIC12F519 FIGURE 8-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) GP3/MCLR/VPP MCLR Reset MCLRE Start-up Timer WDT Reset WDT Time-out Pin Change Sleep S Q R Q (10 μs, 1 ms or 18 ms) CHIP Reset Wake-up on pin Change Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) FIGURE 8-8: VDD MCLR Internal POR TDRT DRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME FIGURE 8-9: VDD MCLR Internal POR TDRT
PIC12F519 FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. DS41319B-page 44 © 2008 Microchip Technology Inc.
PIC12F519 8.5 Device Reset Timer (DRT) On the PIC12F519 device, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 8-5). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize.
PIC12F519 FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 7-1) 0 Watchdog Time 1 M U X Postscaler 8-to-1 MUX PS<2:0> PSA WDT Enable Configuration Bit To Timer0 (Figure 7-3) 0 1 MUX PSA WDT Time-out Note 1: TABLE 8-6: Name OPTION Legend: PSA, PS<2:0> are bits in the OPTION register.
PIC12F519 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF) The TO, PD and (GPWUF) bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset. 8.8.2 The device can wake-up from Sleep through one of the following events: 5. 6. 7.
PIC12F519 8.9 Program Verification/Code Protection FIGURE 8-12: If the code protection bits have not been programmed, the on-chip program and data memory can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read, regardless of the setting of the program memory’s code protection bit. If the code protect bit specific to the FLASH data memory is programmed, then none of the contents of this memory region can be verified externally. 8.
PIC12F519 9.0 INSTRUCTION SET SUMMARY The PIC12F519 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC12F519 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction.
PIC12F519 TABLE 9-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF 12-Bit Opcode Description Cycles MSb LSb Status Notes Affected f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d 0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decrement f 1 Z
PIC12F519 ADDWF Add W and f BCF Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 0≤b≤7 Operation: (W) + (f) → (dest) Operation: 0 → (f) Status Affected: C, DC, Z Status Affected: None Description: Description: Bit ‘b’ in register ‘f’ is cleared.
PIC12F519 BTFSS Bit Test f, Skip if Set CLRW Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW 0 ≤ f ≤ 31 0≤b<7 Operands: None Operation: 00h → (W); 1→Z Operands: Clear W Operation: skip if (f) = 1 Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
PIC12F519 DECF Decrement f INCF Syntax: [ label ] DECF f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: The contents of register ‘f’ are incremented.
PIC12F519 IORWF Inclusive OR W with f MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 (W).OR. (f) → (dest) Operation: (W) → (f) Operation: Status Affected: None Status Affected: Z Description: Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Move data from the W register to register ‘f’.
PIC12F519 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] Syntax: [label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: 00h → WDT; 0 → WDT prescaler; 1 → TO; 0 → PD RETLW k SLEEP Status Affected: None Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC12F519 TRIS Load TRIS Register XORWF Syntax: [ label ] TRIS Syntax: [ label ] XORWF Operands: f=6 Operands: Operation: (W) → TRIS register f 0 ≤ f ≤ 31 d ∈ [0,1] f Exclusive OR W with f f,d Status Affected: None Operation: (W) .XOR. (f) → (dest) Description: TRIS register ‘f’ (f = 6 or 7) is loaded with the contents of the W register. Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’.
PIC12F519 10.
PIC12F519 10.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC12F519 10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC12F519 10.11 PICSTART Plus Development Programmer 10.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC12F519 11.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................... -40°C to +125°C Storage temperature ............................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ...........................................................................................
PIC12F519 PIC12F519 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 11-1: 6.0 INTOSC ONLY 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 4 10 20 25 Frequency (MHz) FIGURE 11-2: MAXIMUM OSCILLATOR FREQUENCY TABLE Oscillator Mode LP XT EXTRC INTOSC 0 200 kHz 4 MHz 8 MHz Frequency (MHz) DS41319B-page 62 © 2008 Microchip Technology Inc.
PIC12F519 11.1 DC Characteristics TABLE 11-1: DC CHARACTERISTICS: PIC12F519 (INDUSTRIAL) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) DC CHARACTERISTICS Param Sym. No. D001 VDD Characteristic Min. Typ(1) Max. 2.0 Supply Voltage (2) Units Conditions 5.5 V See Figure 11-1 D002 VDR RAM Data Retention Voltage — 1.
PIC12F519 TABLE 11-2: DC CHARACTERISTICS: PIC12F519 (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (extended) DC CHARACTERISTICS Param Sym. No. D001 VDD Characteristic Min. Typ(1) Max. 2.0 Supply Voltage (2) 5.5 Units V Conditions See Figure 11-1 D002 VDR RAM Data Retention Voltage — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — Vss — V See Section 8.
PIC12F519 TABLE 11-3: DC CHARACTERISTICS: PIC12F519 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating voltage VDD range as described in DC specification. DC CHARACTERISTICS Param No. Sym. VIL Characteristic Min. Typ† Max. Units Conditions Input Low Voltage I/O ports D030 with TTL buffer D030A Vss — 0.8 V For all 4.5 ≤ VDD ≤ 5.5V Vss — 0.
PIC12F519 TABLE 11-4: VDD (Volts) GP0/GP1 2.0 5.5 GP3 2.0 5.5 DS41319B-page 66 PULL-UP RESISTOR RANGES Temperature (°C) Min. Typ. Max. Units –40 25 85 125 –40 25 85 125 73K 73K 82K 86K 15K 15K 19K 23K 105K 113K 123K 132K 21K 22K 26K 29K 186K 187K 190K 190K 33K 34K 35K 35K Ω Ω Ω Ω Ω Ω Ω Ω –40 25 85 125 –40 25 85 125 63K 77K 82K 86K 16K 16K 24K 26K 81K 93K 96K 100K 20K 21K 25K 27K 96K 116K 116K 119K 22K 23K 28K 29K Ω Ω Ω Ω Ω Ω Ω Ω © 2008 Microchip Technology Inc.
PIC12F519 11.2 Timing Parameter Symbology and Load Conditions – PIC12F519 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC12F519 11.3 AC Characteristics TABLE 11-5: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 11.0 “Electrical Characteristics” Param No. Sym. Characteristic Min. Typ(1) 1A FOSC External CLKIN Frequency(2) DC — 4 DC — 200 DC — 4 MHz EXTRC Oscillator mode 0.
PIC12F519 TABLE 11-6: CALIBRATED INTERNAL RC FREQUENCIES AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 Param No. Freq. Min. Tolerance F10 Sym. FOSC Characteristic Internal Calibrated INTOSC Frequency(1) Typ† Max. Units Conditions ±1% 7.92 8.00 8.08 MHz 3.5V, 25C ±2% 7.84 8.00 8.16 MHz 2.5V ≤ VDD ≤ 5.
PIC12F519 TABLE 11-7: TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) AC CHARACTERISTICS -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Param No. Sym. Characteristic Min. Typ(1) Max.
PIC12F519 TABLE 11-8: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F519 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section TABLE 11-3: “DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)” AC CHARACTERISTICS Param No. Units Conditions Min. 2000* — — ns VDD = 5.0V 9* 9* 18* 18* 30* 40* ms ms VDD = 5.0V (Industrial) VDD = 5.
PIC12F519 TABLE 11-10: TIMER0 CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section TABLE 11-3: “DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)” AC CHARACTERISTICS Param Sym. No. Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period * Note 1: Min.
PIC12F519 12.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC12F519 FIGURE 12-3: IDD vs. VDD OVER FOSC (LP MODE) 120 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 100 32 kHz Maximum Extended IDD (μA) 80 60 32 kHz Maximum Industrial 32 kHz Typical 40 20 0 1 2 3 4 5 6 VDD (V) DS41319B-page 74 © 2008 Microchip Technology Inc.
PIC12F519 FIGURE 12-4: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 0.45 0.40 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.35 IPD (μA) 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) FIGURE 12-5: 18.0 16.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 14.0 Max. 125°C IPD (μA) 12.0 10.0 8.0 6.0 4.0 Max.
PIC12F519 FIGURE 12-6: TYPICAL WDT IPD vs. VDD 9 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 7 IPD (μA) 6 5 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 12-7: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE 25.0 20.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) IPD (μA) Max. 125°C 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC12F519 FIGURE 12-8: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 45 40 Max. 85°C 35 Time (ms) 30 Typical. 25°C 25 20 Min. -40°C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 12-9: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.
PIC12F519 FIGURE 12-10: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C Typical: Statistical Mean @25×C Maximum: Mean (Worst-Case Temp) + 3σ Maximum: Meas(-40×C + 3 to 125×C) (-40°C to 125°C) 0.40 Max. 125°C 0.35 Max. 85°C VOL (V) 0.30 0.25 Typ. 25°C 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 12-11: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.
PIC12F519 FIGURE 12-12: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 12-13: TTL INPUT THRESHOLD VIN vs. VDD 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.
PIC12F519 FIGURE 12-14: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.5 VIH Min. -40°C VIN (V) 3.0 2.5 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 12-15: DEVICE RESET TIMER (XT AND LP) vs. VDD 45 40 35 Max. 125°C DRT (ms) 30 25 Max. 85°C 20 Typical 25°C 15 Min. -40°C 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC12F519 13.0 PACKAGING INFORMATION 13.1 Package Marking Information 8-Lead PDIP Example 12F519-I /P017 0610 XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXX XXXXYYWW NNN 8-Lead MSOP XXXXXX YWWNNN 8-Lead 2x3 DFN* XXX YWW NN e3 * * 12F519-I /SN0610 017 Example 519/MS 610017 Example BY0 610 17 Legend: XX...
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PIC12F519 ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 6 &! ' ! 9 ' &! 7"') % ! β 99 . . 7 7 7: ; < & : 8 & = = = = = # # 4 4 !! & # %% + 1 , : > #& . # # 4 > #& .
PIC12F519 ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS41319B-page 84 © 2008 Microchip Technology Inc.
PIC12F519 ( " ! ) * ( ( ! 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = < = # # 4 4 !! & # %% ? 1 , : > #& . # # 4 > #& .
PIC12F519 + $ ) * (' ,- - %& + 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D e b N N L K E2 E EXPOSED PAD NOTE 1 2 1 NOTE 1 1 2 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 6 &! ' ! 9 ' &! 7"') % ! 99 . .
PIC12F519 + $ ) * (' ,- - %& + 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 © 2008 Microchip Technology Inc.
PIC12F519 APPENDIX A: REVISION HISTORY Revision A (May 2007) Original release of this document. Revision B (September 2008) Added DC and AC Characteristics graphs; Updated Electrical Characteristics section; Updated Package Drawings and made general edits. DS41319B-page 88 © 2008 Microchip Technology Inc.
PIC12F519 INDEX A M ALU ....................................................................................... 9 Assembler MPASM Assembler..................................................... 58 Memory Map PIC12F519 ................................................................. 13 Memory Organization ......................................................... 13 Data EEPROM Memory ............................................. 21 Program Memory (PIC12F519) ..................................
PIC12F519 T Timer0 Timer0 (TMR0) Module ............................................... 31 TMR0 with External Clock........................................... 33 Timing Diagrams and Specifications................................... 67 Timing Parameter Symbology and Load Conditions........... 67 TRIS Registers.................................................................... 23 W Wake-up from Sleep ........................................................... 47 Watchdog Timer (WDT) ........................
PIC12F519 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC12F519 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC12F519 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC12F519 PIC12F519T (Tape and Reel) Temperature Range: I E = = -40°C to +85°C (Industrial) -40°C to +125°C (Extended) Package: MC MS P SN = = = = 8L DFN 2x3 (DUAL Flatpack No-Leads) MSOP (Pb-free) 300 mil PDIP (Pb-free) 3.
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