PIC12F508/509/16F505 Data Sheet 8/14-Pin, 8-Bit Flash Microcontrollers © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC12F508/509/16F505 8/14-Pin, 8-Bit Flash Microcontrollers Devices Included In This Data Sheet: • PIC12F508 • PIC12F509 • PIC16F505 High-Performance RISC CPU: • Only 33 Single-Word Instructions to Learn • All Single-Cycle Instructions Except for Program Branches, which are Two-Cycle • 12-Bit Wide Instructions • 2-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes for Data and Instructions • 8-Bit Wide Data Path • 8 Special Function Hardware Registers • Operating Speed: - DC – 20
PIC12F508/509/16F505 Pin Diagrams PDIP, SOIC, MSOP 14 VSS RB5/OSC1/CLKIN 2 13 RB0/ICSPDAT RB4/OSC2/CLKOUT 3 12 RB1/ICSPCLK RB3/MCLR/VPP 11 RB2 RC5/T0CKI 4 5 10 RC0 RC4 6 9 RC1 RC3 7 8 RC2 PIC16F505 1 VDD VDD 1 GP5/OSC1/CLKIN 2 GP4/OSC2 3 GP3/MCLR/VPP 4 PIC12F508/509 PDIP, SOIC, TSSOP 8 VSS 7 GP0/ICSPDAT 6 GP1/ICSPCLK 5 GP2/T0CKI VDD 1 GP5/OSC1/CLKIN 2 GP4/OSC2 3 GP3/MCLR/VPP 4 PIC12F508/509 DFN 8 VSS 7 GP0/ICSPDAT 6 GP1/ICSPCLK 5 GP2/T0CKI DS41
PIC12F508/509/16F505 Program Memory Data Memory Device I/O Flash (words) SRAM (bytes) Timers 8-bit PIC12F508 512 25 6 1 PIC12F509 1024 41 6 1 PIC16F505 1024 72 12 1 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 Table of Contents 1.0 General Description...................................................................................................................................................................... 7 2.0 PIC12F508/509/16F505 Device Varieties ................................................................................................................................... 9 3.0 Architectural Overview ..............................................................................
PIC12F508/509/16F505 1.0 GENERAL DESCRIPTION The PIC12F508/509/16F505 devices from Microchip Technology are low-cost, high-performance, 8-bit, fully-static, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are single cycle (200 μs) except for program branches, which take two cycles. The PIC12F508/509/16F505 devices deliver performance an order of magnitude higher than their competitors in the same price category.
PIC12F508/509/16F505 NOTES: DS41236E-page 8 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 2.0 PIC12F508/509/16F505 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12F508/509/16F505 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 2.
PIC12F508/509/16F505 NOTES: DS41236E-page 10 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12F508/509/16F505 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12F508/509/16F505 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus.
PIC12F508/509/16F505 FIGURE 3-1: PIC12F508/509 BLOCK DIAGRAM 12 Flash 512 x 12 or 1024 x 12 Program Memory 8 Data Bus Program Counter GP0/ISCPDAT GP1/ISCPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN RAM 25 x 8 or 41 x 8 File Registers Stack 1 Stack 2 Program 12 Bus RAM Addr GPIO 9 Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg Status Reg 8 3 MUX Device Reset Timer Instruction Decode and Control OSC1/CLKIN OSC2 Timing Generation Internal RC OSC Power-on Reset W
PIC12F508/509/16F505 TABLE 3-2: PIC12F508/509 PINOUT DESCRIPTION Name GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN Function Input Type Output Type GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin. GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change.
PIC12F508/509/16F505 FIGURE 3-2: PIC16F505 BLOCK DIAGRAM 12 Flash 1K x 12 Program Memory 8 Data Bus Program Counter RB0/ICSPCLK RB1/ICSPDAT RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN RAM 72 bytes File Registers Stack 1 Stack 2 Program 12 Bus RAM Addr 9 PORTC Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg Status Reg 8 3 Device Reset Timer Instruction Decode and Control OSC1/CLKIN OSC2/CLKOUT Timing Generation PORTB Power-on Reset RC0 RC1 RC2 RC3 RC4 RC5/T0CKI M
PIC12F508/509/16F505 TABLE 3-3: PIC16F505 PINOUT DESCRIPTION Name RB0/ICSPDAT RB1/ICSPCLK Function Input Type Output Type RB0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin. RB1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.
PIC12F508/509/16F505 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g.
PIC12F508/509/16F505 4.0 MEMORY ORGANIZATION The PIC12F508/509/16F505 memories are organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the PIC12F509 and PIC16F505, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).
PIC12F508/509/16F505 4.2 Program Memory Organization For The PIC16F505 The PIC16F505 device has a 11-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. The 1K x 12 (0000h-03FFh) for the PIC16F505 are physically implemented. Refer to Figure 4-2. Accessing a location above this boundary will cause a wrap-around within the first 1K x 12 space. The effective Reset vector is at 0000h (see Figure 4-2). Location 03FFh contains the internal oscillator calibration value.
PIC12F508/509/16F505 FIGURE 4-3: PIC12F508 REGISTER FILE MAP FIGURE 4-4: PIC12F509 REGISTER FILE MAP FSR<5> File Address 0 1 File Address 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h OSCCAL 06h GPIO 07h 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h OSCCAL 06h GPIO 20h Addresses map back to addresses in Bank 0.
PIC12F508/509/16F505 4.3.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
PIC12F508/509/16F505 TABLE 4-2: Address SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset(2) Page # 00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 28 01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 35 02h(1) PCL Low-order 8 bits of PC 1111 1111 27 03h STATUS RBWUF 0-01 1xxx 22 Indirect Data Memory Address Pointer 04h FSR 05h OSCCAL 06h 07h — PA0 CAL4
PIC12F508/509/16F505 4.4 STATUS Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits from the STATUS register.
PIC12F508/509/16F505 REGISTER 4-2: STATUS REGISTER (ADDRESS: 03h) (PIC16F505) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x RBWUF — PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBWUF: PORTB Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 Reserved: Do not use bit 5 PA0: Program Page Prese
PIC12F508/509/16F505 4.5 OPTION Register The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. Note: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU/RBPU and GPWU/RBWU). Note: If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin.
PIC12F508/509/16F505 REGISTER 4-4: OPTION REGISTER (PIC16F505) W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 clock Source
PIC12F508/509/16F505 4.6 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4 MHz oscillator. It contains seven bits for calibration. Note: After you move in the calibration constant, do not change the value. See Section 7.2.5 “Internal 4 MHz RC Oscillator”. Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator.
PIC12F508/509/16F505 4.7 4.7.1 Program Counter EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction).
PIC12F508/509/16F505 4.9 EXAMPLE 4-1: Indirect Data Addressing: INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. 4.9.
PIC12F508/509/16F505 FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505) Direct Addressing (FSR) 6 5 Bank Select 4 Indirect Addressing (opcode) 0 6 Location Select 01 10 00h (FSR) 0 Location Select 11 Addresses map back to addresses in Bank 0. 0Fh 10h 1Fh Bank 0 Note 1: 4 Bank 00 Data Memory(1) 5 3Fh Bank 1 5Fh Bank 2 7Fh Bank 3 For register map detail, see Section 4.3 “Data Memory Organization”. © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 NOTES: DS41236E-page 30 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 5.0 I/O PORT As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set. Note: 5.1 On the PIC12F508/509, I/O PORTB is referenced as GPIO. On the PIC16F505, I/O PORTB is referenced as PORTB.
PIC12F508/509/16F505 TABLE 5-1: Address SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 TRISGPIO(1) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on All Other Resets — — I/O Control Register --11 1111 --11 1111 N/A (2) TRISB — — I/O Control Register --11 1111 --11 1111 N/A TRISC(2) — — I/O Control Register --11 1111 --11 1111 N/A OPTION(1) GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A OPTION(2) RBWU RBPU TOCS TOSE PSA PS2 PS1
PIC12F508/509/16F505 5.5 I/O Programming Considerations 5.5.1 BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs.
PIC12F508/509/16F505 NOTES: DS41236E-page 34 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 6.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1 “Using Timer0 with an External Clock”.
PIC12F508/509/16F505 FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Counter) Instruction Fetch MOVWF TMR0 T0 Timer0 T0 + 1 Instruction Executed 01h NT0 Write TMR0 executed TABLE 6-1: Address MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 Read TMR0
PIC12F508/509/16F505 6.1 Using Timer0 with an External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
PIC12F508/509/16F505 6.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section 7.6 “Watchdog Timer (WDT)”). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice versa.
PIC12F508/509/16F505 BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER(1), (2) FIGURE 6-5: TCY (= FOSC/4) Data Bus 0 (GP2/RC5)/T0CKI pin 1 8 M U X 1 M U X 0 T0SE T0CS 0 Watchdog Timer 1 M U X Sync 2 Cycles TMR0 Reg PSA 8-bit Prescaler 8 8-to-1 MUX PS<2:0> PSA WDT Enable bit 1 0 MUX PSA WDT Time-out Note 1: 2: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509. © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 NOTES: DS41236E-page 40 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 7.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC12F508/509/16F505 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection.
PIC12F508/509/16F505 REGISTER 7-1: — — CONFIGURATION WORD FOR PIC12F508/509(1) — — — — — MCLRE CP WDTE FOSC1 bit 11 FOSC0 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 11-5 Unimplemented: Read as ‘0’ bit 4 MCLRE: GP3/MCLR Pin Function Select bit 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital input, MCLR internally tied to VDD bit 3 CP: Code Protection bit 1 = Cod
PIC12F508/509/16F505 REGISTER 7-2: — — CONFIGURATION WORD FOR PIC16F505(1) — — — — MCLRE CP WDTE FOSC2 FOSC1 bit 11 FOSC0 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 11-6 Unimplemented: Read as ‘0’ bit 5 MCLRE: RB3/MCLR Pin Function Select bit 1 = RB3/MCLR pin function is MCLR 0 = RB3/MCLR pin function is digital input, MCLR internally tied to VDD bit 4 CP: Code Protection bit 1 = Code
PIC12F508/509/16F505 7.2 7.2.1 Oscillator Configurations FIGURE 7-1: OSCILLATOR TYPES The PIC12F508/509/16F505 devices can be operated in up to six different oscillator modes. The user can program up to three Configuration bits (FOSC<1:0> [PIC12F508/509], FOSC<2:0> [PIC16F505]).
PIC12F508/509/16F505 TABLE 7-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR – PIC12F508/509/16F505(2) Osc Type Resonator Freq. Cap. Range C1 Cap. Range C2 LP 32 kHz(1) 15 pF 15 pF XT 200 kHz 1 MHz 4 MHz 47-68 pF 15 pF 15 pF 47-68 pF 15 pF 15 pF 20 MHz 15-47 pF 15-47 pF HS(3) Note 1: 2: 3: 7.2.3 FIGURE 7-3: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To Other Devices 10k For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended. These values are for design guidance only.
PIC12F508/509/16F505 Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. Section 10.0 “Electrical Characteristics” shows RC frequency variation from part-to-part due to normal process variation.
PIC12F508/509/16F505 7.3 Reset The device differentiates between various kinds of Reset: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT time-out Reset during normal operation WDT time-out Reset during Sleep Wake-up from Sleep on pin change TABLE 7-3: Register Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset.
PIC12F508/509/16F505 TABLE 7-4: RESET CONDITIONS FOR REGISTERS – PIC16F505 Register Address W — Power-on Reset MCLR Reset, WDT Time-out, Wake-up On Pin Change qqqq qqqu(1) qqqq qqqu(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu(2), (3) FSR 04h 100x xxxx 1uuu uuuu OSCCAL 05h 1111 111- uuuu uuu- PORTB 06h --xx xxxx --uu uuuu PORTC 07h --xx xxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRISB —
PIC12F508/509/16F505 7.3.1 MCLR ENABLE This Configuration bit, when unprogrammed (left in the ‘1’ state), enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD and the pin is assigned to be an input only. See Figure 7-6. FIGURE 7-6: MCLR SELECT GPWU/RBWU (GP3/RB3)/MCLR/VPP Internal MCLR MCLRE 7.
PIC12F508/509/16F505 FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) (GP3/RB3)/MCLR/VPP MCLR Reset MCLRE WDT Reset WDT Time-out S Q R Q Start-up Timer CHIP Reset (10 μs or 18 ms) Pin Change Sleep Wake-up on pin Change Reset FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME FIGURE 7-9: VDD MCLR Intern
PIC12F508/509/16F505 FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 7.5 Device Reset Timer (DRT) On the PIC12F508/509/16F505 devices, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 7-6). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize.
PIC12F508/509/16F505 FIGURE 7-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 6-5) 0 1 Watchdog Time M U X Postscaler 8-to-1 MUX PS<2:0> PSA WDT Enable Configuration Bit To Timer0 (Figure 6-4) 0 1 MUX PSA WDT Time-out Note 1: TABLE 7-7: Address T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
PIC12F508/509/16F505 7.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF/RBWUF) FIGURE 7-13: VDD VDD The TO, PD and (GPWUF/RBWUF) bits in the STATUS register can be tested to determine if a Reset condition has been caused by a Power-up condition, a MCLR or Watchdog Timer (WDT) Reset.
PIC12F508/509/16F505 7.9 Power-down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep). 7.9.1 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off.
PIC12F508/509/16F505 FIGURE 7-15: External Connector Signals TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections PIC16F505 PIC12F508 PIC12F509 +5V VDD 0V VSS VPP MCLR/VPP CLK GP1/RB1 Data I/O GP0/RB0 VDD To Normal Connections DS41236E-page 56 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 8.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction.
PIC12F508/509/16F505 TABLE 8-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF 12-Bit Opcode Description Cycles MSb LSb Status Notes Affected f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d 0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decr
PIC12F508/509/16F505 ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 0≤b≤7 Operation: (W) + (f) → (dest) Operation: 0 → (f) Status Affected: C, DC, Z Status Affected: None Description: Description: Bit ‘b’ in register ‘f’ is cleared. BSF Bit Set f ANDLW Syntax: f,d Add the contents of the W register and register ‘f’. If ‘d’ is’0’, the result is stored in the W register.
PIC12F508/509/16F505 BTFSS Bit Test f, Skip if Set CLRW Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW 0 ≤ f ≤ 31 0≤b<7 Operands: None Operation: 00h → (W); 1→Z Operands: Clear W Operation: skip if (f) = 1 Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
PIC12F508/509/16F505 DECF Decrement f INCF Syntax: [ label ] DECF f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: The contents of register ‘f’ are incremented.
PIC12F508/509/16F505 IORWF Inclusive OR W with f MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 Operation: (W).OR. (f) → (dest) (W) → (f) Operation: Status Affected: None Status Affected: Z Description: Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Move data from the W register to register ‘f’.
PIC12F508/509/16F505 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] Syntax: [label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: Status Affected: None Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC12F508/509/16F505 TRIS Load TRIS Register XORWF Syntax: [ label ] TRIS Syntax: [ label ] XORWF Operands: f=6 Operands: Operation: (W) → TRIS register f 0 ≤ f ≤ 31 d ∈ [0,1] f Exclusive OR W with f f,d Status Affected: None Operation: (W) .XOR. (f) → (dest) Description: TRIS register ‘f’ (f = 6 or 7) is loaded with the contents of the W register Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’.
PIC12F508/509/16F505 9.
PIC12F508/509/16F505 9.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC12F508/509/16F505 9.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC12F508/509/16F505 9.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket.
PIC12F508/509/16F505 10.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................... -40°C to +125°C Storage temperature ............................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................
PIC12F508/509/16F505 PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 10-1: 6.0 5.5 (PIC16F505 only) 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 25 Frequency (MHz) FIGURE 10-2: MAXIMUM OSCILLATOR FREQUENCY TABLE Oscillator Mode LP XT INTOSC EXTRC EC(1) HS(1) 0 200 kHz 4 MHz 20 MHz Frequency (MHz) Note 1: DS41236E-page 70 For PIC16F505 only. © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) DC Characteristics Param Sym. No. D001 VDD Characteristic Supply Voltage VDR D003 VPOR VDD Start Voltage to ensure Power-on Reset D004 SVDD VDD Rise Rate to ensure Power-on Reset IDD D020 IPD D022 IWDT * Note 1: 2: 3: 4: 5: Typ(1) Max. 2.0 (2) D002 D010 Min. RAM Data Retention Voltage 5.
PIC12F508/509/16F505 10.2 DC Characteristics: PIC12F508/509/16F505 (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (extended) DC Characteristics Param No. Sym. D001 VDD Characteristic Supply Voltage D002 VDR VPOR VDD Start Voltage to ensure Power-on Reset D004 SVDD VDD Rise Rate to ensure Power-on Reset IDD D020 IPD D022 IWDT * Note 1: 2: 3: 4: 5: Typ(1) Max. 2.0 (2) D003 D010 Min. RAM Data Retention Voltage 5.
PIC12F508/509/16F505 TABLE 10-1: DC CHARACTERISTICS: PIC12F508/509/16F505 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating voltage VDD range as described in DC specification DC CHARACTERISTICS Param No. Sym. VIL Characteristic Min. Typ† Max. Units Conditions Input Low Voltage I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer Vss — 0.
PIC12F508/509/16F505 TABLE 10-2: VDD (Volts) PULL-UP RESISTOR RANGES – PIC12F508/509/16F505 Temperature (°C) GP0(RBO)/GP1(RB1) 2.0 5.5 GP3(RB3) 2.0 5.5 * –40 25 85 125 –40 25 85 125 Min. Typ. Max. 73K 73K 82K 86K 15K 15K 19K 23K 105K 113K 123K 132k 21K 22K 26k 29K 186K 187K 190K 190K 33K 34K 35K 35K 81K 93K 96k 100K 20k 21K 25k 27K 96K 116K 116K 119K 22K 23K 28K 29K –40 63K 25 77K 85 82K 125 86K –40 16K 25 16K 85 24K 125 26K These parameters are characterized but not tested.
PIC12F508/509/16F505 10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC12F508/509/16F505 TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505 AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 "Poweron Reset (POR)" Param No. Sym. Characteristic Min.
PIC12F508/509/16F505 TABLE 10-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC12F508/509/16F505 AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Param No. Freq Min. Tolerance F10 Sym. FOSC Characteristic Internal Calibrated INTOSC Frequency(1) Typ† Max. Units Conditions ± 1% 3.96 4.00 4.04 MHz VDD = 3.5V, TA = 25°C ± 2% 3.92 4.00 4.08 MHz 2.5V ≤ VDD ≤ 5.
PIC12F508/509/16F505 TABLE 10-5: TIMING REQUIREMENTS – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) AC Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) CHARACTERISTICS -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 "Power-on Reset (POR)" Param No. 17 Sym. TOSH2IOV Characteristic Min. Typ(1) Max.
PIC12F508/509/16F505 TABLE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) AC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ(1) Max. Units 30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 5.0V 31 TWDT Watchdog Timer Time-out Period (no prescaler) 9* 9* 18* 18* 30* 40* ms ms VDD = 5.0V (Industrial) VDD = 5.
PIC12F508/509/16F505 FIGURE 10-7: TIMER0 CLOCK TIMINGS – PIC12F508/509/16F505 T0CKI 40 41 42 TABLE 10-7: TIMER0 CLOCK REQUIREMENTS – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 "Power-on Reset (POR)" AC CHARACTERISTICS Param Sym. No.
PIC12F508/509/16F505 11.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC12F508/509/16F505 FIGURE 11-2: IDD VS. FOSC Over VDD (HS MODE, PIC16F505 only) 3.00 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 2.50 Max. 5V IDD (mA) 2.00 Typical 5V 1.50 1.00 Max. 3V 0.50 Typical 3V 0.00 10 5 15 25 20 Fosc (MHz) FIGURE 11-3: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.
PIC12F508/509/16F505 FIGURE 11-4: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 16.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 14.0 Max. 125°C IPD (μA) 12.0 10.0 8.0 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) TYPICAL WDT IPD vs.
PIC12F508/509/16F505 FIGURE 11-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 20.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) IPD (μA) Max. 125°C 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) WDT TIME-OUT or DEVICE RESET TIMER vs. VDD OVER TEMPERATURE (NO WDT PRESCALER)(1) FIGURE 11-7: 50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 45 40 Max.
PIC12F508/509/16F505 FIGURE 11-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.7 Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 11-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.
PIC12F508/509/16F505 FIGURE 11-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 11-11: (VDD = 5.0V) VOH vs. IOH OVER TEMPERATURE ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.
PIC12F508/509/16F505 FIGURE 11-12: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) VIH Min.
PIC12F508/509/16F505 FIGURE 11-14: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (25°C) 55 44 Change from Calibration (%) 33 22 11 00 -1-1 -2-2 -3-3 -4-4 -5-5 22 2.5 2.5 3 3 44 3.5 3.5 5 4.5 4.5 5.5 5.5 VDD (V) TYPICAL INTOSC FREQUENCY CHANGE vs VDD (-40°C) FIGURE 11-15: 55 44 Change from Calibration (%) 33 22 11 00 -1-1 -2-2 -3-3 -4-4 -5-5 22 2.5 2.5 33 3.5 3.5 44 4.5 4.5 55 5.5 5.5 VDD (V) DS41236E-page 88 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 FIGURE 11-16: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (85°C) 5 44 Change from Calibration (%) 33 22 11 00 -1-1 -2-2 -3-3 -4 -4 -5-5 22 2.5 2.5 33 3.5 3.5 44 4.5 4.5 5 5.5 5.5 VDD (V) FIGURE 11-17: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (125°C 5 44 Change from Calibration (%) 33 22 11 00 -1-1 -2-2 -3-3 -4 -4 -5-5 22 2.5 2.5 33 3.5 3.5 44 4.5 4.5 55 5.5 5.5 VDD (V) © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 NOTES: DS41236E-page 90 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 12.0 PACKAGING INFORMATION 12.1 Package Marking Information 8-Lead PDIP Example XXXXXXXX XXXXXNNN YYWW 12F508-I /P e3 017 0610 8-Lead SOIC (3.90 mm) XXXXXXXX XXXXYYWW NNN 8-Lead MSOP 8-Lead 2x3 DFN* XXX YWW NN Example Example BEQ 610 17 Legend: XX...
PIC12F508/509/16F505 12.1 Package Marking Information (Continued) 14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (3.90 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.
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PIC12F508/509/16F505 ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 ( " ! ) * ( ( ! 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = < = # # 4 4 !! & # %% ? 1 , : > #& . # # 4 > #& .
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PIC12F508/509/16F505 ./ 01 1" ) ! 0 /%/ 0 ! 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 e b c φ A2 A A1 L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; & : 8 & = = < = # # 4 4 !! & # %% ? 1 , : > #& . # # 4 > #& .
PIC12F508/509/16F505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41236E-page 102 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 APPENDIX A: REVISION HISTORY Revision A (April 2004) Original devices data sheet for PIC12F508/509/16F505 Revision B (June 2005) Update packages Revision C (03/2007) Revised Table 3-2 Legend; Revised Table 3-3 RB3 and Legend; Revised Table 10-4 F10; Replaced Package Drawings (Rev. AN); Added DFN package; Replaced Development Support Section; Revised Product ID System. Revision D (12/2007) Revised Title; Operating Current; Table 1-1 added DFN and revised note; Revised Section 3.
PIC12F508/509/16F505 NOTES: DS41236E-page 104 © 2009 Microchip Technology Inc.
PIC12F508/509/16F505 INDEX A ALU ..................................................................................... 11 Assembler MPASM Assembler..................................................... 66 MPLAB Integrated Development Environment Software.... 65 MPLAB PM3 Device Programmer ...................................... 67 MPLAB REAL ICE In-Circuit Emulator System .................. 67 MPLINK Object Linker/MPLIB Object Librarian .................. 66 B O Block Diagram On-Chip Reset Circuit .......
PIC12F508/509/16F505 W Wake-up from Sleep ........................................................... 55 Watchdog Timer (WDT) ................................................ 41, 52 Period.......................................................................... 52 Programming Considerations ..................................... 52 WWW Address.................................................................. 107 WWW, On-Line Support........................................................ 6 Z Zero bit .....
PIC12F508/509/16F505 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC12F508/509/16F505 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC12F508/509/16F505 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F505 PIC12F508 PIC12F509 PIC16F505T(1) PIC12F508T(2) PIC12F509T(2) Temperature Range: I E Package: MC MS P SL SN ST MG Pattern: Note: = = c) PIC12F508-E/P 301 = Extended Temp., PDIP package, QTP pattern #301 PIC12F508-I/SN = Industrial Temp.
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