Datasheet

PIC12(L)F1840
DS41441C-page 78  2011-2012 Microchip Technology Inc.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0
OSFIF
— C1IF EEIF BCL1IF — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 Unimplemented: Read as ‘0’
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2-0 Unimplemented: Read as ‘0’
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 151
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 75
PIE2
OSFIE
— C1IE EEIE BCL1IE — — —
76
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
77
PIR2
OSFIF
— C1IF EEIF BCL1IF — — —
78
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.