Datasheet

PIC12(L)F1840
DS41441C-page 46  2011-2012 Microchip Technology Inc.
5.2.2.5 Internal Oscillator Frequency
Selection
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The output of the 16 MHz HFINTOSC postscaler and
LFINTOSC connects to a multiplexer (see Figure 5-1).
The Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register select the
frequency output of the internal oscillators. One of the
following frequencies can be selected via software:
• 32 MHz (requires 4x PLL)
•16 MHz
•8 MHz
•4 MHz
•2 MHz
•1 MHz
• 500 kHz (default after Reset)
• 250 kHz
• 125 kHz
• 62.5 kHz
• 31.25 kHz
• 31 kHz (LFINTOSC)
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli-
cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi-
tion times can be obtained between frequency changes
that use the same oscillator source.
5.2.2.6 32 MHz Internal Oscillator
Frequency Selection
The Internal Oscillator Block can be used with the 4x
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz inter-
nal clock source:
• The FOSC bits in Configuration Words must be
set to use the INTOSC source as the device sys-
tem clock (FOSC<2:0> = 100).
• The SCS bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<2:0> in Configuration Words
(SCS<1:0> = 00).
• The IRCF bits in the OSCCON register must be
set to the 8 MHz HFINTOSC set to use
(IRCF<3:0> = 1110).
• The SPLLEN bit in the OSCCON register must be
set to enable the 4xPLL, or the PLLEN bit of the
Configuration Words must be programmed to a
‘1’.
The 4x PLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4x PLL with the internal oscillator.
Note: Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
Note: When using the PLLEN bit of the
Configuration Words, the 4x PLL cannot
be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.