Datasheet

PIC12(L)F1840
DS41441C-page 404  2011-2012 Microchip Technology Inc.
Timer2
T2CON.............................................................. 167
Timing Diagrams
Acknowledge Sequence ........................................... 241
ADC Conversion ....................................................... 335
ADC Conversion (Sleep Mode)................................. 336
Asynchronous Reception .......................................... 264
Asynchronous Transmission..................................... 260
Asynchronous Transmission (Back to Back) ............ 260
Auto Wake-up Bit (WUE) During Normal Operation . 277
Auto Wake-up Bit (WUE) During Sleep .................... 277
Automatic Baud Rate Calibration.............................. 275
Baud Rate Generator with Clock Arbitration ............. 234
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 245
Brown-out Reset (BOR) ............................................ 331
Brown-out Reset Situations ........................................63
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................ 246
Bus Collision During a Repeated Start Condition
(Case 2) ............................................................ 247
Bus Collision During a Start Condition (SCL = 0) .....245
Bus Collision During a Stop Condition (Case 1) ....... 248
Bus Collision During a Stop Condition (Case 2) ....... 248
Bus Collision During Start Condition (SDA only) ...... 244
Bus Collision for Transmit and Acknowledge............ 243
CLKOUT and I/O....................................................... 330
Clock Synchronization ..............................................231
Clock Timing ............................................................. 328
Comparator Output ...................................................141
Enhanced Capture/Compare/PWM (ECCP) ............. 334
Fail-Safe Clock Monitor (FSCM) ................................. 53
First Start Bit Timing .................................................235
Half-Bridge PWM Output .................................. 190, 193
I
2
C Bus Data.............................................................343
I
2
C Bus Start/Stop Bits..............................................342
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 238
I
2
C Master Mode (7-Bit Reception)........................... 240
I
2
C Stop Condition Receive or Transmit Mode ......... 242
INT Pin Interrupt.......................................................... 72
Internal Oscillator Switch Timing................................. 48
PWM Auto-shutdown ................................................192
Firmware Restart ..............................................191
PWM Output (Active-High)........................................ 189
PWM Output (Active-Low) ........................................ 189
Repeat Start Condition.............................................. 236
Reset Start-up Sequence............................................ 65
Reset, WDT, OST and Power-up Timer ................... 331
Send Break Character Sequence ............................. 278
SPI Master Mode (CKE = 1, SMP = 1) ..................... 339
SPI Mode (Master Mode).......................................... 208
SPI Slave Mode (CKE = 0) ....................................... 340
SPI Slave Mode (CKE = 1) ....................................... 340
Synchronous Reception (Master Mode, SREN) ....... 282
Synchronous Transmission....................................... 280
Synchronous Transmission (Through TXEN) ........... 280
Timer0 and Timer1 External Clock ........................... 333
Timer1 Incrementing Edge........................................ 157
Two Speed Start-up .................................................... 51
USART Synchronous Receive (Master/Slave) ......... 338
USART Synchronous Transmission (Master/Slave) . 338
Wake-up from Interrupt ............................................... 80
Timing Diagrams and Specifications
PLL Clock.................................................................. 329
Timing Parameter Symbology...........................................327
Timing Requirements
I
2
C Bus Data............................................................. 343
SPI Mode.................................................................. 341
TMR0 Register.................................................................... 22
TMR1H Register................................................................. 22
TMR1L Register.................................................................. 22
TMR2 Register.................................................................... 22
TRIS.................................................................................. 312
TRISA Register........................................................... 22, 105
Two-Speed Clock Start-up Mode........................................ 50
TXREG ............................................................................. 259
TXREG Register................................................................. 23
TXSTA Register.......................................................... 23, 267
BRGH Bit .................................................................. 270
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 338
Requirements, Synchronous Transmission...... 338
Timing Diagram, Synchronous Receive ........... 338
Timing Diagram, Synchronous Transmission... 338
V
VREF. SEE ADC Reference Voltage
VREGCON Register ........................................................... 82
W
Wake-up on Break ............................................................ 276
Wake-up Using Interrupts ................................................... 80
Watchdog Timer (WDT)...................................................... 64
Associated Registers.................................................. 86
Configuration Word w/ Watchdog Timer..................... 86
Modes......................................................................... 84
Specifications ........................................................... 332
WCOL ....................................................... 234, 237, 239, 241
WCOL Status Flag.................................... 234, 237, 239, 241
WDTCON Register ............................................................. 85
WPUB Register................................................................. 107
Write Protection .................................................................. 37
WWW Address ................................................................. 405
WWW, On-Line Support ................................................... 2, 5