Datasheet

 2011-2012 Microchip Technology Inc. DS41441C-page 19
PIC12(L)F1840
TABLE 3-3: PIC12(L)F1840 MEMORY MAP (CONTINUED)
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Tab l e 3 - 2)
480h
48Bh
Core Registers
(Tab l e 3 - 2)
500h
50Bh
Core Registers
(Tab l e 3 - 2)
580h
58Bh
Core Registers
(Tab l e 3 - 2)
600h
60Bh
Core Registers
(Tab l e 3 - 2)
680h
68Bh
Core Registers
(Tab l e 3 - 2)
700h
70Bh
Core Registers
(Tab l e 3 - 2)
780h
78Bh
Core Registers
(Tab l e 3 - 2)
40Ch
Unimplemented
Read as ‘0’
48Ch
Unimplemented
Read as ‘0’
50Ch
Unimplemented
Read as ‘0’
58Ch
Unimplemented
Read as ‘0’
60Ch
Unimplemented
Read as ‘0’
68Ch
Unimplemented
Read as ‘0’
70Ch
Unimplemented
Read as ‘0’
78Ch
Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Common RAM
(Accesses
70h – 7Fh)
4F0h
Common RAM
(Accesses
70h – 7Fh)
570h
Common RAM
(Accesses
70h – 7Fh)
5F0h
Common RAM
(Accesses
70h – 7Fh)
670h
Common RAM
(Accesses
70h – 7Fh)
6F0h
Common RAM
(Accesses
70h – 7Fh)
770h
Common RAM
(Accesses
70h – 7Fh)
7F0h
Common RAM
(Accesses
70h – 7Fh)
47Fh
4FFh 57Fh
5FFh 67Fh 6FFh 77Fh 7FFh
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Tab l e 3 - 2)
880h
88Bh
Core Registers
(Tab l e 3 - 2)
900h
90Bh
Core Registers
(Tab l e 3 - 2)
980h
98Bh
Core Registers
(Tab l e 3 - 2)
A00h
A0Bh
Core Registers
(Tab l e 3 - 2)
A80h
A8Bh
Core Registers
(Tab l e 3 - 2)
B00h
B0Bh
Core Registers
(Tab l e 3 - 2)
B80h
B8Bh
Core Registers
(Tab l e 3 - 2)
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh
9EFh
A6Fh
AEFh
B6Fh
BEFh
870h
Common RAM
(Accesses
70h – 7Fh)
8F0h
Common RAM
(Accesses
70h – 7Fh)
970h
Common RAM
(Accesses
70h – 7Fh)
9F0h
Common RAM
(Accesses
70h – 7Fh)
A70h
Common RAM
(Accesses
70h – 7Fh)
AF0h
Common RAM
(Accesses
70h – 7Fh)
B70h
Common RAM
(Accesses
70h – 7Fh)
BF0h
Common RAM
(Accesses
70h – 7Fh)
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30
C00h
C0Bh
Core Registers
(Tab l e 3 - 2)
C80h
C8Bh
Core Registers
(Tab l e 3 - 2)
D00h
D0Bh
Core Registers
(Tab l e 3 - 2)
D80h
D8Bh
Core Registers
(Tab l e 3 - 2)
E00h
E0Bh
Core Registers
(Tab l e 3 - 2)
E80h
E8Bh
Core Registers
(Tab l e 3 - 2)
F00h
F0Bh
Core Registers
(Tab l e 3 - 2)
C0Ch
C6Fh
Unimplemented
Read as ‘0’
C8Ch
CEFh
Unimplemented
Read as ‘0’
D0Ch
D6Fh
Unimplemented
Read as ‘0’
D8Ch
DEFh
Unimplemented
Read as ‘0’
E0Ch
E6Fh
Unimplemented
Read as ‘0’
E8Ch
EEFh
Unimplemented
Read as ‘0’
F0Ch
F6Fh
Unimplemented
Read as ‘0’
C70h
Common RAM
(Accesses
70h – 7Fh)
CF0h
Common RAM
(Accesses
70h – 7Fh)
D70h
Common RAM
(Accesses
70h – 7Fh)
DF0h
Common RAM
(Accesses
70h – 7Fh)
E70h
Common RAM
(Accesses
70h – 7Fh)
EF0h
Common RAM
(Accesses
70h – 7Fh)
F70h
Common RAM
(Accesses
70h – 7Fh)
C7Fh
CFFh D7Fh DFFh E7Fh EFFh F7Fh