Datasheet

PIC12(L)F1840
DS41441C-page 140  2011-2012 Microchip Technology Inc.
TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE
REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
SRSPE SRSCKE
Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7
SRSPE: SR Latch Peripheral Set Enable bit
1 = SR latch is set when the SRI pin is high
0 = SRI pin has no effect on the set input of the SR latch
bit 6
SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with SRCLK
0 = SRCLK has no effect on the set input of the SR latch
bit 5
Reserved: Read as ‘0’. Maintain this bit clear.
bit 4
SRSC1E: SR Latch C1 Set Enable bit
1 = SR latch is set when the C1 Comparator output is high
0 = C1 Comparator output has no effect on the set input of the SR latch
bit 3
SRRPE: SR Latch Peripheral Reset Enable bit
1 = SR latch is reset when the SRI pin is high
0 = SRI pin has no effect on the reset input of the SR latch
bit 2
SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR latch is pulsed with SRCLK
0 = SRCLK has no effect on the reset input of the SR latch
bit 1
Reserved: Read as ‘0’. Maintain this bit clear.
bit 0
SRRC1E: SR Latch C1 Reset Enable bit
1 = SR latch is reset when the C1 Comparator output is high
0 = C1 Comparator output has no effect on the reset input of the SR latch
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 139
SRCON1 SRSPE SRSCKE
Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E 140
TRISA
— —TRISA5TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
105
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR Latch module.