Datasheet

 2011-2012 Microchip Technology Inc. DS41441C-page 139
PIC12(L)F1840
18.4 Register Definitions: SR Latch Control
REGISTER 18-1: SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0
SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only
bit 7 SRLEN: SR Latch Enable bit
1 = SR Latch is enabled
0 = SR Latch is disabled
bit 6-4 SRCLK<2:0>: SR Latch Clock Divider bits
111 = Generates a 1 F
OSC wide pulse every 512th FOSC cycle clock
110 = Generates a 1 F
OSC wide pulse every 256th FOSC cycle clock
101 = Generates a 1 F
OSC wide pulse every 128th FOSC cycle clock
100 = Generates a 1 F
OSC wide pulse every 64th FOSC cycle clock
011 = Generates a 1 F
OSC wide pulse every 32nd FOSC cycle clock
010 = Generates a 1 F
OSC wide pulse every 16th FOSC cycle clock
001 = Generates a 1 F
OSC wide pulse every 8th FOSC cycle clock
000 = Generates a 1 F
OSC wide pulse every 4th FOSC cycle clock
bit 3 SRQEN: SR Latch Q Output Enable bit
If SRLEN =
1:
1 = Q is present on the SRQ pin
0 = External Q output is disabled
If SRLEN =
0:
SR Latch is disabled
bit 2 SRNQEN: SR Latch Q
Output Enable bit
If SRLEN =
1:
1 =Q
is present on the SRnQ pin
0 = External Q
output is disabled
If SRLEN =
0:
SR Latch is disabled
bit 1 SRPS: Pulse Set Input of the SR Latch bit
(1)
1 = Pulse set input for 1 Q-clock period
0 = No effect on set input.
bit 0 SRPR: Pulse Reset Input of the SR Latch bit
(1)
1 = Pulse reset input for 1 Q-clock period
0 = No effect on Reset input.
Note 1: Set only, always reads back ‘0’.