Datasheet

 2011-2013 Microchip Technology Inc. DS40001441D-page 249
PIC12(L)F1840
TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 75
PIE2
OSFIE — C1IE EEIE BCL1IE
—
— — 76
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
77
PIR2
OSFIF
—
C1IF EEIF BCL1IF — —
— 78
SSP1ADD ADD<7:0> 255
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 205*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 252
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 253
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 254
SSP1MSK MSK<7:0> 255
SSP1STAT SMP CKE
D/A P S R/W UA BF 251
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 105
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I
2
C™ mode.
* Page provides register information.