Datasheet

 2011-2013 Microchip Technology Inc. DS40001441D-page 231
PIC12(L)F1840
25.5.6 CLOCK STRETCHING
Clock stretching occurs when a device on the bus
holds the SCL line low effectively pausing
communication. The slave may stretch the clock to
allow more time to handle data or prepare a response
for the master device. A master device is not
concerned with stretching as anytime it is active on the
bus and not transferring data it is stretching. Any
stretching done by a slave is invisible to the master
software and handled by the hardware that generates
SCL.
The CKP bit of the SSP1CON1 register is used to con-
trol stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
25.5.6.1 Normal Clock Stretching
Following an ACK
if the R/W bit of SSP1STAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSP1BUF with data to
transfer to the master. If the SEN bit of SSP1CON2 is
set, the slave hardware will always stretch the clock
after the ACK
sequence. Once the slave is ready; CKP
is set by software and communication resumes.
25.5.6.2 10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set, the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSP1ADD.
25.5.6.3 Byte NACKing
When AHEN bit of SSP1CON3 is set; CKP is cleared
by hardware after the 8th falling edge of SCL for a
received matching address byte. When DHEN bit of
SSP1CON3 is set; CKP is cleared after the 8th falling
edge of SCL for received data.
Stretching after the 8th falling edge of SCL allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSP1BUF was read before the 9th falling
edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSP1BUF was loaded before the 9th fall-
ing edge of SCL. It is now always cleared
for read requests.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.