Datasheet

2011-2013 Microchip Technology Inc. DS40001441D-page 23
PIC12(L)F1840
Bank 2
10Ch LATA —LATA5LATA4—LATA2LATA1LATA0--xx -xxx --uu -uuu
10Dh
to
110h
Unimplemented
111h CM1CON0 C1ON C1OUT C1OE C1POL
C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1 C1INTP C1INTN C1PCH<1:0>
C1NCH 0000 ---0 0000 ---0
113h
Unimplemented
114h
Unimplemented
115h CMOUT
—MC1OUT---- ---0 ---- ---0
116h BORCON SBOREN BORFS
BORRDY 10-- ---q uu-- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN DACLPS DACOE
DACPSS<1:0> 000- 00-- 000- 00--
119h DACCON1
DACR<4:0> ---0 0000 ---0 0000
11Ah SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh SRCON1 SRSPE SRSCKE
Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E 0000 0000 0000 0000
11Ch
Unimplemented
11Dh APFCON RXDTSEL SDOSEL SSSEL
--- T1GSEL TXCKSEL P1BSEL CCP1SEL 000- 0000 000- 0000
11Eh
Unimplemented
11Fh
Unimplemented
Bank 3
18Ch ANSELA ANSA4 ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
18Dh
to
190h
Unimplemented
191h EEADRL EEPROM/Program Memory Address Register Low Byte 0000 0000 0000 0000
192h EEADRH
(3)
EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000
193h EEDATL EEPROM/Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH
EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000
197h VREGCON
(2)
—VREGPMReserved ---- --01 ---- --01
198h
Unimplemented
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL
SCKP BRG16 —WUEABDEN01-0 0-00 01-0 0-00
TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as0’.
Note 1: These registers can be addressed from any bank.
2: PIC12F1840 only.
3: Unimplemented, read as1’.