Datasheet

 2011-2013 Microchip Technology Inc. DS40001441D-page 181
PIC12(L)F1840
24.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (F
OSC/4), or by an external clock source.
When Timer1 is clocked by F
OSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
24.1.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
reset, see
Section 12.1 “Alternate Pin Function” for
more information.
TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON RXDTSEL SDOSEL SSSEL
—
T1GSEL TXCKSEL P1BSEL CCP1SEL
102
CCP1CON
P1M<1:0> DC1B<1:0> CCP1M<3:0>
197
CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB)
180
CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB)
180
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
74
PIE1 TMR1GIE
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
75
PIE2 OSFIE
—
C1IE EEIE BCL1IE — — — 76
PIR1 TMR1GIF
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
77
PIR2
OSFIF
— C1IF EEIF BCL1IF — —
— 78
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
—TMR1ON
161
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0>
162
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
157*
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
157*
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
105
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.
* Page provides register information.