Information

 2012-2013 Microchip Technology Inc. DS80538B-page 3
PIC12(L)F1840
Silicon Errata Issues
1. Module: Oscillator
1.1 OSCSTAT bits: HFIOFR and HFIOFS
When HFINTOSC is selected, the HFIOFR and
HFIOFS bits will become set when the oscillator
becomes ready and stable. Once these bits are set
they become “stuck”, indicating that HFINTOSC is
always ready and stable. If the HFINTOSC is
disabled, the bits fail to be cleared.
Work around
None.
Affected Silicon Revisions
1.2 Clock Switching
When switching clock sources between INTOSC
clock source and an external clock source
operating at a different power mode, one corrupted
instruction may be executed after the switch
occurs.
This issue does not affect Two-Speed Start-up or
the Fail-Safe Clock Monitor operation.
Work around
When clock switching from an external oscillator
clock source, first switch to 16 MHz HFINTOSC.
Once running at 16 MHz HFINTOSC, configure
IRCF to run at desired frequency.
When clock switching from an INTOSC to an
external oscillator clock source, first switch from
desired INTOSC frequency to HFINTOSC
High-Power mode (8 MHz or 16 MHz). Once
running from HFINTOSC, switch to the external
oscillator clock source.
Affected Silicon Revisions
1.3 Oscillator Start-up Timer (OST) bit
During the Two-Speed Start-up sequence, the
OST is enabled to count 1024 clock cycles. After
the count is reached, the OSTS bit is set, the sys-
tem clock is held low until the next falling edge of
the external crystal (LP, XT or HS mode), before
switching to the external clock source.
When an external oscillator is configured as the
primary clock and Fail-Safe Clock mode is enabled
(FCMEN = 1), any of the following conditions will
result in the Oscillator Start-up Timer (OST) failing
to restart:
•MCLR
Reset
• Wake from Sleep
• Clock change from INTOSC to Primary Clock
This anomaly will manifest itself as a clock failure
condition for external oscillators which take longer
than the clock failure time-out period to start.
Work around
None.
Affected Silicon Revisions
2. Module: Resets
2.1 Low-Power Sleep (PIC12F1840 device only)
When the device is in low-power Sleep (VREGPM
= 1 and SLEEP instruction is executed), a MCLR
Reset will be reported as a POR Reset:
•PD
= 1
•POR
= 0
• RDMCLR
= 1
Work around
Use Normal-Power Sleep mode (VREGPM = 0).
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A5).
A4 A5
X
A4 A5
X
A4 A5
X
A4 A5
X X