Datasheet

PIC12(L)F1840
DS40001441D-page 138  2011-2013 Microchip Technology Inc.
FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM
TABLE 18-1: SRCLK FREQUENCY TABLE
SRPS
S
R
Q
Q
Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
2:
Pulse generator causes a 1 Q-state pulse width.
3: Name denotes the connection point at the comparator output.
Pulse
Gen
(2)
SR
Latch
(1)
SRQEN
SRSPE
SRSCKE
SRCLK
SRSC1E
sync_C1OUT
(3)
SRPR
Pulse
Gen
(2)
SRRPE
SRRCKE
SRCLK
SRRC1E
sync_C1OUT
(3)
SRLEN
SRNQEN
SRLEN
SRQ
SRNQ
SRI
SRI
SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz
111 512 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz
110 256 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz
101 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz
100 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz
011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz
010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz
001 8 4 MHz 2.5 MHz 2 MHz 500 kHz 125 kHz
000 4 8 MHz 5 MHz 4 MHz 1 MHz 250 kHz