Datasheet

PIC12(L)F1571/2
DS40001723D-page 80  2013-2015 Microchip Technology Inc.
REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0 R-0/0 R-0/0 R-0/0 U-0 U-0 U-0 U-0
—PWM3IF
(1)
PWM2IF
(1)
PWM1IF
(1)
— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6 PWM3IF: PWM3 Interrupt Flag bit
(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 PWM2IF: PWM2 Interrupt Flag bit
(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 PWM1IF: PWM1 Interrupt Flag bit
(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3-0 Unimplemented: Read as ‘0’
Note 1: These bits are read-only. They must be cleared by addressing the Flag registers inside the module.
2: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.