Datasheet

PIC12(L)F1571/2
DS40001723D-page 72  2013-2015 Microchip Technology Inc.
FIGURE 7-3: INT PIN INTERRUPT TIMING
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
FOSC
CLKOUT
INT Pin
INTF
GIE
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
(2)
PC
PC + 1
PC + 1 0004h 0005h
Inst (0004h)
Inst (0005h)
Forced NOP
Inst (PC)
Inst (PC + 1)
Inst (PC – 1)
Inst (0004h)
Forced NOP
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 T
CY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: For minimum width of INT pulse, refer to AC specifications in Section 26.0 “Electrical Specifications”.
4: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(3)
(4)
(1)
INSTRUCTION FLOW