Datasheet

PIC12(L)F1571/2
DS40001723D-page 60  2013-2015 Microchip Technology Inc.
6.1 Power-on Reset (POR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising V
DD, fast operating speeds or analog
performance may require greater than minimum V
DD.
The PWRT, BOR or MCLR
features can be used to
extend the start-up period until all device operation
conditions have been met.
6.1.1 POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms
time-out on a POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the V
DD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in the Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00000607).
6.2 Brown-out Reset (BOR)
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in the
Configuration Words. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to Table 6-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in the Configuration Words.
A V
DD noise rejection filter prevents the BOR from trig-
gering on small events. If V
DD falls below VBOR for a
duration greater than parameter, T
BORDC, the device
will reset. See Figure 6-2 for more information.
TABLE 6-1: BOR OPERATING MODES
BOREN<1:0> SBOREN Device Mode BOR Mode
Instruction Execution upon:
Release of POR or Wake-up from Sleep
11 X XActive
Waits for BOR ready
(1)
(BORRDY = 1)
10 X
Awake Active Waits for BOR ready
(BORRDY = 1)
Sleep Disabled
01
1 XActive
Waits for BOR ready
(1)
(BORRDY = 1)
0 X Disabled Begins immediately
(BORRDY = x)
00 X X Disabled
Note 1: In these specific cases, “release of POR” and “wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.