Datasheet

 2013-2015 Microchip Technology Inc. DS40001723D-page 55

PIC12(L)F1571/2

5.5 Register Definitions: Oscillator Control

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0

SPLLEN IRCF<3:0> —SCS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit

u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words =

SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements).

If PLLEN in Configuration Words = 0:

1 = 4x PLL Is enabled

0 = 4x PLL is disabled

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 = 16 MHz HF

1110 = 8 MHz or 32 MHz HF (see Section 5.2.2.1 “HFINTOSC”)

1101 = 4 MHz HF

1100 = 2 MHz HF

1011 = 1 MHz HF

1010 = 500 kHz HF

(1)

1001 = 250 kHz HF

(1)

1000 = 125 kHz HF

(1)

0111 = 500 kHz MF (default upon Reset)

0110 = 250 kHz MF

0101 = 125 kHz MF

0100 = 62.5 kHz MF

0011 = 31.25 kHz HF

(1)

0010 = 31.25 kHz MF

000x = 31 kHz LF

bit 2 Unimplemented: Read as ‘0’

bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block

01 = Timer1 oscillator

00 = Clock determined by FOSC<1:0> in Configuration Words

Note 1: Duplicate frequency derived from HFINTOSC.