Datasheet

PIC12(L)F1571/2
DS40001723D-page 54  2013-2015 Microchip Technology Inc.
5.3 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCSx) bits of the OSCCON
register. The following clock sources can be selected
using the SCSx bits:
• Default system oscillator determined by FOSCx
bits in the Configuration Words
• Timer1 32 kHz crystal oscillator
• Internal Oscillator Block (INTOSC)
5.3.1 SYSTEM CLOCK SELECT (SCSx)
BITS
The System Clock Select (SCSx) bits of the OSCCON
register select the system clock source that is used for
the CPU and peripherals.
• When the SCSx bits of the OSCCON register = 00,
the system clock source is determined by the value
of the FOSC<1:0> bits in the Configuration Words.
• When the SCSx bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
• When the SCSx bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0> bits
of the OSCCON register. After a Reset, the SCSx
bits of the OSCCON register are always cleared.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 5-1.
5.4 Clock Switching Before Sleep
When clock switching from an old clock to a new clock
is requested, just prior to entering Sleep mode, it is
necessary to confirm that the switch is complete before
the SLEEP instruction is executed. Failure to do so may
result in an incomplete switch and consequential loss of
the system clock altogether. Clock switching is
confirmed by monitoring the clock status bits in the
OSCSTAT register. Switch confirmation can be accom-
plished by sensing that the ready bit for the new clock is
set or the ready bit for the old clock is cleared. For
example, when switching between the internal oscillator
with the PLL and the internal oscillator without the PLL,
monitor the PLLR bit. When PLLR is set, the switch to
32 MHz operation is complete. Conversely, when PLLR
is cleared, the switch from 32 MHz operation to the
selected internal clock is complete.
TABLE 5-1: OSCILLATOR SWITCHING DELAYS
Note: Any automatic clock switch does not
update the SCSx bits of the OSCCON
register. The user can monitor the OSTS
bit of the OSCSTAT register to determine
the current system clock source.
Switch From Switch To Frequency Oscillator Delay
Sleep/POR
LFINTOSC
(1)
MFINTOSC
(1)
HFINTOSC
(1)
31 kHz
31.25 kHz-500 kHz
31.25kHz-16MHz
Oscillator Warm-up Delay (T
WARM)
(2)
Sleep/POR EC
(1)
DC – 32 MHz 2 cycles
LFINTOSC EC
(1)
DC – 32 MHz 1 cycle of each
Any Clock Source
MFINTOSC
(1)
HFINTOSC
(1)
31.25 kHz-500 kHz
31.25kHz-16MHz
2 s (approx.)
Any Clock Source LFINTOSC
(1)
31 kHz 1 cycle of each
PLL Inactive PLL Active 16-32 MHz 2 ms (approx.)
Note 1: PLL inactive.
2: See Section 26.0 “Electrical Specifications”.