Datasheet

PIC12(L)F1571/2
DS40001723D-page 52  2013-2015 Microchip Technology Inc.
5.2.2.7 32 MHz Internal Oscillator
Frequency Selection
The internal oscillator block can be used with the
4x PLL associated with the external oscillator block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz
internal clock source:
• The FOSCx bits in the Configuration Words must
be set to use the INTOSC source as the device
system clock (FOSC<1:0> = 00).
• The SCSx bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<1:0> in the Configuration Words
(SCS<1:0> = 00).
• The IRCFx bits in the OSCCON register must be
set to the 8 MHz HFINTOSC to use
(IRCF<3:0> = 1110).
• The SPLLEN bit in the OSCCON register must be
set to enable the 4x PLL or the PLLEN bit of the
Configuration Words must be programmed to a
‘1’.
The 4x PLL is not available for use with the internal
oscillator when the SCSx bits of the OSCCON register
are set to ‘1x’. The SCSx bits must be set to ‘00’ to use
the 4x PLL with the internal oscillator.
5.2.2.8 Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 5-3). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
1. IRCF<3:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
See Figure 5-3 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
Start-up delay specifications are located in the
oscillator tables of Section 26.0 “Electrical
Specifications”.
Note: When using the PLLEN bit of the
Configuration Words, the 4x PLL cannot
be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.