Datasheet

PIC12(L)F1571/2
DS40001723D-page 282  2013-2015 Microchip Technology Inc.
FIGURE 26-13: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 26-17: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 26-14: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 26-18: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
US120 T
CKH2DTV SYNC XMIT (Master and Slave)
Clock High to Data-Out Valid
—80ns3.0V  V
DD  5.5V
— 100 ns 1.8V  V
DD  5.5V
US121 T
CKRF Clock Out Rise Time and Fall Time
(Master mode)
—45ns3.0V  VDD  5.5V
—50ns1.8V  V
DD  5.5V
US122 TDTRF Data-Out Rise Time and Fall Time — 45 ns 3.0V  VDD  5.5V
—50ns1.8V  VDD  5.5V
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
US125 T
DTV2CKL SYNC RCV (Master and Slave)
Data-Hold before CK  (DT hold time) 10 — ns
US126 T
CKL2DTL Data-Hold after CK  (DT hold time) 15 — ns
Note: Refer to Figure 26-4 for load conditions.
US121
US121
US120
US122
CK
DT
Note: Refer to Figure 26-4 for load conditions.
US125
US126
CK
DT