Datasheet

 2013-2015 Microchip Technology Inc. DS40001723D-page 27
PIC12(L)F1571/2
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 0
00Ch PORTA — — RA<5:0> --xx xxxx --xx xxxx
00Dh — Unimplemented — —
00Eh
— Unimplemented — —
00Fh
— Unimplemented — —
010h
— Unimplemented — —
011h PIR1 TMR1GIF ADIF RCIF
(2)
TXIF
(2)
— — TMR2IF TMR1IF 0000 --00 0000 --00
012h PIR2 — —C1IF — — — — — --0- ---- --0- ----
013h PIR3 — PWM3IF PWM2IF PWM1IF — — — — -000 ---- -000 ----
014h — Unimplemented — —
015h TMR0 Holding Register for the 8-Bit Timer0 Count
xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Count xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Count xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> —T1SYNC —TMR1ON 0000 -0-0 uuuu -u-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
01Dh — Unimplemented — —
01Eh
— Unimplemented — —
01Fh
— Unimplemented — —
Bank 1
08Ch TRISA — — TRISA<5:4> —
(2)
TRISA<2:0> --11 1111 --11 1111
08Dh — Unimplemented — —
08Eh
— Unimplemented — —
08Fh
— Unimplemented — —
090h
— Unimplemented — —
091h PIE1 TMR1GIE ADIE RCIE
(2)
TXIE
(2)
— — TMR2IE TMR1IE 0000 --00 0000 --00
092h PIE2 — —C1IE— — — — — --0- ---- --0- ----
093h PIE3 — PWM3IE PWM2IE PWM1IE — — — — -000 ---- -000 ----
094h — Unimplemented — —
095h OPTION_REG WPUEN
INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF —RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu
097h WDTCON — —WDTPS<4:0>SWDTEN --01 0110 --01 0110
098h OSCTUNE — —TUN<5:0> --00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0> —SCS<1:0> 0011 1-00 0011 1-00
09Ah OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS -0q0 0q00 -qqq qqqq
09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00
09Fh ADCON2 TRIGSEL<3:0> — — — — 0000 ---- 0000 ----
Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘ 0 ’.
Note 1: PIC12F1571/2 only.
2: PIC12(L)F1572 only.
3: Unimplemented, read as ‘ 1 ’.