Datasheet

 2013-2015 Microchip Technology Inc. DS40001723D-page 221

PIC12(L)F1571/2

U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0

— OFM<1:0> OFO

(1)

— —OFS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit

u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets

bit 7 Unimplemented: Read as ‘0’

bit 6-5 OFM<1:0>: Offset Mode Select bits

11 = Continuous Slave Run mode with immediate Reset and synchronized start when the selected

offset trigger occurs

10 = One-Shot Slave Run mode with synchronized start when the selected offset trigger occurs

01 = Independent Slave Run mode with synchronized start when the selected offset trigger occurs

00 = Independent Run mode

bit 4 OFO: Offset Match Output Control bit

(1)

If MODE<1:0> = 11 (PWM Center-Aligned mode):

1 = OFx_match occurs on counter match when counter decrementing, (second match)

0 = OFx_match occurs on counter match when counter incrementing, (first match)

If MODE<1:0> =

00, 01 or 10 (all other modes):

Bit is ignored.

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 OFS<1:0>: Offset Trigger Source Select bits

11 =OF3_match

(1)

10 =OF2_match

(1)

01 =OF1_match

(1)

00 = Reserved

Note 1: The OFx_match corresponding to the PWM used becomes reserved.