Datasheet

PIC12(L)F1571/2
DS40001723D-page 220  2013-2015 Microchip Technology Inc.
REGISTER 22-5: PWMxLDCON: PWMx RELOAD TRIGGER SOURCE SELECT REGISTER
R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
LDA
(1)
LDT — — — —LDS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 LDA: Load Buffer Armed bit
(1)
If LDT = 1:
1 = Loads the OFx, PHx, DCx and PRx buffers at the end of the period when the selected trigger occurs
0 = Does not load buffers or load has completed
If LDT =
0:
1 = Loads the OFx, PHx, DCx and PRx buffers at the end of the current period
0 = Does not load buffers or load has completed
bit 6 LDT: Load Buffer on Trigger bit
1 = Loads buffers on trigger enabled
0 = Loads buffers on trigger disabled
Loads the OFx, PHx, DCx and PRx buffers at the end of every period after the selected trigger occurs.
Reloads internal double buffers at the end of current period. The LDS<1:0> bits are ignored.
bit 5-2 Unimplemented: Read as ‘0’
bit 1-0 LDS<1:0>: Load Trigger Source Select bits
11 = LD3_trigger
(2)
10 = LD2_trigger
(2)
01 = LD1_trigger
(2)
00 = Reserved
Note 1: This bit is cleared by the module after a reload operation. It can be cleared in software to clear an existing
arming event.
2: The LD_trigger corresponding to the PWM used becomes reserved.