Datasheet

PIC12(L)F1571/2
DS40001723D-page 218  2013-2015 Microchip Technology Inc.
REGISTER 22-3: PWMxINTF: PWMx INTERRUPT REQUEST REGISTER
U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — — — OFIF PHIF DCIF PRIF
bit 7 bit 0
Legend:
HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-4 Unimplemented: Read as ‘0’
bit 3 OFIF: Offset Interrupt Flag bit
(1)
1 = Offset match event occurred
0 = Offset match event did not occur
bit 2 PHIF: Phase Interrupt Flag bit
(1)
1 = Phase match event occurred
0 = Phase match event did not occur
bit 1 DCIF: Duty Cycle Interrupt Flag bit
(1)
1 = Duty cycle match event occurred
0 = Duty cycle match event did not occur
bit 0 PRIF: Period Interrupt Flag bit
(1)
1 = Period match event occurred
0 = Period match event did not occur
Note 1: Bit is forced clear by hardware while module is disabled (EN = 0).