Datasheet

PIC12(L)F1571/2
DS40001723D-page 200  2013-2015 Microchip Technology Inc.
21.5.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in Transmit mode; otherwise,
the device will be configured to receive. Setting the SPEN
bit of the RCSTA register enables the EUSART.
21.5.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and
Slave modes is identical (see Section 21.5.1.3
“Synchronous Master Transmission”), except in the
case of Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in the TXREG
register.
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the
second character to the TSR and the TXIF bit
will now be set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
21.5.2.2 Synchronous Slave Transmission
Setup
1. Set the SYNC and SPEN bits, and clear the
CSRC bit.
2. Clear the ANSELx bit for the CK pin (if applicable).
3. Clear the CREN and SREN bits.
4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TXREG register.
TABLE 21-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUDCON
ABDOVF RCIDL —SCKPBRG16 — WUE ABDEN 186
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE
(1)
TXIE
(1)
— — TMR2IE TMR1IE 75
PIR1
TMR1GIF ADIF RCIF
(1)
TXIF
(1)
— — TMR2IF TMR1IF 78
RCSTA SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 185
TXREG EUSART Transmit Data Register 177*
TXSTA CSRC TX9 TXEN SYNC SENDB
BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
* Page provides register information.
Note 1: PIC12(L)F1572 only.