Datasheet

 2013-2015 Microchip Technology Inc. DS40001723D-page 199
PIC12(L)F1571/2
FIGURE 21-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 21-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1
TMR1GIE ADIE RCIE
(1)
TXIE
(1)
— — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF
(1)
TXIF
(1)
— — TMR2IF TMR1IF 78
RCREG EUSART Receive Data Register 180*
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 185
SPBRGL BRG<7:0> 187*
SPBRGH BRG<15:8> 187*
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
CREN bit
RX/DT
Write to
SREN bit
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK Pin
TX/CK Pin
Pin
(SCKP = 0)
(SCKP = 1)